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test
# 56 JMJS    09.7.20 16:00

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 327
97  test plusargs value plusargs JMJS 24.9.5 346
96  color text JMJS 24.7.13 383
95  draw_hexa.v JMJS 10.6.17 2539
94  jmjsxram3.v JMJS 10.4.9 2431
93  Verilog document JMJS 11.1.24 3029
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2620
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4055
90  gtkwave PC version JMJS 09.3.30 2418
89  ncsim option example JMJS 08.12.1 4785
88  [영상]keywords for web search JMJS 08.12.1 2384
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6544
86  ncverilog option example JMJS 10.6.8 8243
85  [Verilog]Latch example JMJS 08.12.1 2985
84  Pad verilog example JMJS 01.3.16 4920
83  [ModelSim] vector JMJS 01.3.16 2611
82  RTL Code 분석순서 JMJS 09.4.29 2859
81  [temp]PIPE JMJS 08.10.2 2255
80  [temp]always-forever 무한루프 JMJS 08.10.2 2333
79  YCbCr2RGB.v JMJS 10.5.12 2530
78  [VHDL]rom64x8 JMJS 09.3.27 2078
77  [function]vector_compare JMJS 02.6.19 1978
76  [function]vector2integer JMJS 02.6.19 2182
75  [VHDL]ram8x4x8 JMJS 08.12.1 1917
74  [예]shift JMJS 02.6.19 2372
73  test JMJS 09.7.20 2215
72  test JMJS 09.7.20 1789
71  test JMJS 09.7.20 1929
70  test JMJS 09.7.20 2025
69  test JMJS 09.7.20 2072
68  test JMJS 09.7.20 2005
67  test JMJS 09.7.20 1942
66  test JMJS 09.7.20 1888
65  test JMJS 09.7.20 2007
64  test JMJS 09.7.20 2203
63  test JMJS 09.7.20 2238
62  test JMJS 09.7.20 2131
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3923
60  test JMJS 09.7.20 1722
59  test JMJS 09.7.20 2059
58  test JMJS 09.7.20 1966
57  test JMJS 09.7.20 1933
56  test JMJS 09.7.20 1974
55  verilog 학과 샘플강의 JMJS 16.5.30 2428
54  [verilog]create_generated_clock JMJS 15.4.28 2409
53  [Verilog]JDIFF JMJS 14.7.4 1796
52  [verilog]parameter definition JMJS 14.3.5 2083
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5019
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2684
49  Verdi JMJS 10.4.22 3561
48  draw hexa JMJS 10.4.9 2072
47  asfifo - Async FIFO JMJS 10.4.8 1934
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3607
45  synplify batch JMJS 10.3.8 2800
44  전자시계 Type A JMJS 08.11.28 2293
43  I2C Webpage JMJS 08.2.25 2128
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6239
41  [Verilog]vstring JMJS 17.9.27 2334
40  Riviera Simple Case JMJS 09.4.29 3429
39  [VHDL]DES Example JMJS 07.6.15 3280
38  [verilog]RAM example JMJS 09.6.5 3059
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2293
36  Jamie's VHDL Handbook JMJS 08.11.28 2987
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3566
34  RTL Job JMJS 09.4.29 2498
33  [VHDL]type example - package TYPES JMJS 06.2.2 1970
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9634
30  [verilog]array_module JMJS 05.12.8 2536
29  [verilog-2001]generate JMJS 05.12.8 3681
28  protected JMJS 05.11.18 2332
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3081
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2071
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2703
23  Array Of Array JMJS 04.8.16 2226
22  dumpfile, dumpvars JMJS 04.7.19 3919
21  Vending Machine Jamie 02.12.16 10357
20  Mini Vending Machine1 Jamie 02.12.10 7226
19  Mini Vending Machine Jamie 02.12.6 10061
18  Key Jamie 02.11.29 5258
17  Stop Watch Jamie 02.11.25 5810
16  Mealy Machine Jamie 02.8.29 6976
15  Moore Machine Jamie 02.8.29 18328
14  Up Down Counter Jamie 02.8.29 4347
13  Up Counter Jamie 02.8.29 3040
12  Edge Detecter Jamie 02.8.29 3252
11  Concept4 Jamie 02.8.28 2229
10  Concept3 Jamie 02.8.28 2319
9  Concept2_1 Jamie 02.8.28 2217
8  Concept2 Jamie 02.8.28 2301
7  Concept1 Jamie 02.8.26 2352
6  Tri State Buffer Jamie 02.8.26 3896
5  8x3 Encoder Jamie 02.8.28 4448
4  3x8 Decoder Jamie 02.8.28 4090
3  4bit Comparator Jamie 02.8.26 3470
2  가위 바위 보 게임 Jamie 02.8.26 5646
1  Two Input Logic Jamie 02.8.26 2720
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