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Concept2
# 8 Jamie    02.8.28 16:01

1.Spec

con signal이 '1'일 경우 입력 data를 출력합니다.
source에서는 정의하지 않은 con signal이 '0'일 때는 출력 data가 기존의 data값을
그대로 유지하고 있습니다.
즉, 두 번째 컨셉은 latch입니다.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept2.vhd
  Test Vector : concept2_tb.vhd
게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2065
94  jmjsxram3.v JMJS 10.4.9 1799
93  Verilog document JMJS 11.1.24 2370
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1948
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3418
90  gtkwave PC version JMJS 09.3.30 1749
89  ncsim option example JMJS 08.12.1 4127
88  [영상]keywords for web search JMJS 08.12.1 1760
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6074
86  ncverilog option example JMJS 10.6.8 7440
85  [Verilog]Latch example JMJS 08.12.1 2363
84  Pad verilog example JMJS 01.3.16 4272
83  [ModelSim] vector JMJS 01.3.16 1965
82  RTL Code 분석순서 JMJS 09.4.29 2259
81  [temp]PIPE JMJS 08.10.2 1627
80  [temp]always-forever 무한루프 JMJS 08.10.2 1709
79  YCbCr2RGB.v JMJS 10.5.12 1911
78  [VHDL]rom64x8 JMJS 09.3.27 1521
77  [function]vector_compare JMJS 02.6.19 1490
76  [function]vector2integer JMJS 02.6.19 1558
75  [VHDL]ram8x4x8 JMJS 08.12.1 1434
74  [예]shift JMJS 02.6.19 1789
73  test JMJS 09.7.20 1570
72  test JMJS 09.7.20 1380
71  test JMJS 09.7.20 1313
70  test JMJS 09.7.20 1423
69  test JMJS 09.7.20 1450
68  test JMJS 09.7.20 1374
67  test JMJS 09.7.20 1296
66  test JMJS 09.7.20 1254
65  test JMJS 09.7.20 1361
64  test JMJS 09.7.20 1624
63  test JMJS 09.7.20 1610
62  test JMJS 09.7.20 1538
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3325
60  test JMJS 09.7.20 1294
59  test JMJS 09.7.20 1377
58  test JMJS 09.7.20 1402
57  test JMJS 09.7.20 1333
56  test JMJS 09.7.20 1383
55  verilog 학과 샘플강의 JMJS 16.5.30 2001
54  [verilog]create_generated_clock JMJS 15.4.28 1967
53  [Verilog]JDIFF JMJS 14.7.4 1250
52  [verilog]parameter definition JMJS 14.3.5 1509
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4415
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2230
49  Verdi JMJS 10.4.22 2805
48  draw hexa JMJS 10.4.9 1595
47  asfifo - Async FIFO JMJS 10.4.8 1421
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3052
45  synplify batch JMJS 10.3.8 2173
44  전자시계 Type A JMJS 08.11.28 1673
43  I2C Webpage JMJS 08.2.25 1540
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5673
41  [Verilog]vstring JMJS 17.9.27 1776
40  Riviera Simple Case JMJS 09.4.29 2912
39  [VHDL]DES Example JMJS 07.6.15 2659
38  [verilog]RAM example JMJS 09.6.5 2436
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1696
36  Jamie's VHDL Handbook JMJS 08.11.28 2354
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2975
34  RTL Job JMJS 09.4.29 1818
33  [VHDL]type example - package TYPES JMJS 06.2.2 1511
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9031
30  [verilog]array_module JMJS 05.12.8 1892
29  [verilog-2001]generate JMJS 05.12.8 3080
28  protected JMJS 05.11.18 1710
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2532
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1607
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2148
23  Array Of Array JMJS 04.8.16 1691
22  dumpfile, dumpvars JMJS 04.7.19 3316
21  Vending Machine Jamie 02.12.16 9776
20  Mini Vending Machine1 Jamie 02.12.10 6585
19  Mini Vending Machine Jamie 02.12.6 9416
18  Key Jamie 02.11.29 4668
17  Stop Watch Jamie 02.11.25 5391
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14  Up Down Counter Jamie 02.8.29 3677
13  Up Counter Jamie 02.8.29 2455
12  Edge Detecter Jamie 02.8.29 2654
11  Concept4 Jamie 02.8.28 1796
10  Concept3 Jamie 02.8.28 1759
9  Concept2_1 Jamie 02.8.28 1635
8  Concept2 Jamie 02.8.28 1715
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6  Tri State Buffer Jamie 02.8.26 3221
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1  Two Input Logic Jamie 02.8.26 2157
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