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Concept2
# 8 Jamie    02.8.28 16:01

1.Spec

con signalÀÌ '1'ÀÏ °æ¿ì ÀÔ·Â data¸¦ Ãâ·ÂÇÕ´Ï´Ù.
source¿¡¼­´Â Á¤ÀÇÇÏÁö ¾ÊÀº con signalÀÌ '0'ÀÏ ¶§´Â Ãâ·Â data°¡ ±âÁ¸ÀÇ data°ªÀ»
±×´ë·Î À¯ÁöÇϰí ÀÖ½À´Ï´Ù.
Áï, µÎ ¹øÂ° ÄÁ¼ÁÀº latchÀÔ´Ï´Ù.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept2.vhd
  Test Vector : concept2_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 166
97  test plusargs value plusargs JMJS 24.9.5 232
96  color text JMJS 24.7.13 239
95  draw_hexa.v JMJS 10.6.17 2440
94  jmjsxram3.v JMJS 10.4.9 2166
93  Verilog document JMJS 11.1.24 2767
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2320
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3777
90  gtkwave PC version JMJS 09.3.30 2102
89  ncsim option example JMJS 08.12.1 4494
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2119
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6442
86  ncverilog option example JMJS 10.6.8 7917
85  [Verilog]Latch example JMJS 08.12.1 2715
84  Pad verilog example JMJS 01.3.16 4637
83  [ModelSim] vector JMJS 01.3.16 2315
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2616
81  [temp]PIPE JMJS 08.10.2 1976
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2055
79  YCbCr2RGB.v JMJS 10.5.12 2272
78  [VHDL]rom64x8 JMJS 09.3.27 1869
77  [function]vector_compare JMJS 02.6.19 1819
76  [function]vector2integer JMJS 02.6.19 1891
75  [VHDL]ram8x4x8 JMJS 08.12.1 1784
74  [¿¹]shift JMJS 02.6.19 2142
73  test JMJS 09.7.20 1926
72  test JMJS 09.7.20 1714
71  test JMJS 09.7.20 1644
70  test JMJS 09.7.20 1739
69  test JMJS 09.7.20 1786
68  test JMJS 09.7.20 1715
67  test JMJS 09.7.20 1635
66  test JMJS 09.7.20 1603
65  test JMJS 09.7.20 1709
64  test JMJS 09.7.20 1938
63  test JMJS 09.7.20 1942
62  test JMJS 09.7.20 1862
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3668
60  test JMJS 09.7.20 1645
59  test JMJS 09.7.20 1739
58  test JMJS 09.7.20 1709
57  test JMJS 09.7.20 1656
56  test JMJS 09.7.20 1702
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2316
54  [verilog]create_generated_clock JMJS 15.4.28 2307
53  [Verilog]JDIFF JMJS 14.7.4 1573
52  [verilog]parameter definition JMJS 14.3.5 1836
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4794
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2571
49  Verdi JMJS 10.4.22 3267
48  draw hexa JMJS 10.4.9 1922
47  asfifo - Async FIFO JMJS 10.4.8 1758
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3394
45  synplify batch JMJS 10.3.8 2498
44  ÀüÀڽðè Type A JMJS 08.11.28 2010
43  I2C Webpage JMJS 08.2.25 1860
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6021
41  [Verilog]vstring JMJS 17.9.27 2102
40  Riviera Simple Case JMJS 09.4.29 3232
39  [VHDL]DES Example JMJS 07.6.15 2991
38  [verilog]RAM example JMJS 09.6.5 2755
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2034
36  Jamie's VHDL Handbook JMJS 08.11.28 2690
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3338
34  RTL Job JMJS 09.4.29 2178
33  [VHDL]type example - package TYPES JMJS 06.2.2 1841
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9380
30  [verilog]array_module JMJS 05.12.8 2314
29  [verilog-2001]generate JMJS 05.12.8 3404
28  protected JMJS 05.11.18 2073
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 2883
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 1914
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2505
23  Array Of Array JMJS 04.8.16 2005
22  dumpfile, dumpvars JMJS 04.7.19 3625
21  Vending Machine Jamie 02.12.16 10100
20  Mini Vending Machine1 Jamie 02.12.10 6979
19  Mini Vending Machine Jamie 02.12.6 9826
18  Key Jamie 02.11.29 5001
17  Stop Watch Jamie 02.11.25 5697
16  Mealy Machine Jamie 02.8.29 6754
15  Moore Machine Jamie 02.8.29 17980
14  Up Down Counter Jamie 02.8.29 4087
13  Up Counter Jamie 02.8.29 2787
12  Edge Detecter Jamie 02.8.29 2992
11  Concept4 Jamie 02.8.28 2128
10  Concept3 Jamie 02.8.28 2086
9  Concept2_1 Jamie 02.8.28 1966
8  Concept2 Jamie 02.8.28 2055
7  Concept1 Jamie 02.8.26 2271
6  Tri State Buffer Jamie 02.8.26 3561
5  8x3 Encoder Jamie 02.8.28 4180
4  3x8 Decoder Jamie 02.8.28 3852
3  4bit Comparator Jamie 02.8.26 3231
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5571
1  Two Input Logic Jamie 02.8.26 2474
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