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Component¹®Àº ÀÌ¹Ì ¼³°èÇÑ Entity¸¦ ºÎǰÀ¸·Î °£ÁÖÇÏ¿© ±¸Á¶ÀûÀ¸·Î ¼³°è Çϱâ À§ÇØ ÇÊ¿äÇÑ ¹®ÀÔ´Ï´Ù. ArchitectureÇ¥ÇöÀÇ ¹®Àå¸Ó¸®¿Í Begin»çÀÌ¿¡ Component¸¦ ¼±¾ðÇϰí, Port map()À̶õ ¿¹¾à¾î¸¦ »ç¿ëÇÏ¿© Component¸¦ »ç·ÊÈ ½Ãŵ´Ï´Ù.
Example>
--componentÈ ÇÒ entity 1
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(a, b : in std_logic;
c : out std_logic);
end or2;
architecture JMJS_Logic of or2 is
begin
c <= a or b;
end JMJS_Logic;
--componentÈ ÇÒ entity 2
library ieee;
use ieee.std_logic_1164.all;
entity HA is
port(x, y : in std_logic;
c, s : out std_logic);
end HA;
architecture JMJS_Logic of HA is
begin
process(x, y)
begin
if(x=¡¯1¡¯) and (y=¡¯1¡¯) then
c <= ¡®1¡¯;
else
c <= ¡®0¡¯;
end if;
end process;
process(x, y)
begin
if(x=y) then
s <= ¡®0¡¯;
else
s <= ¡®1¡¯;
end if;
end process;
end JMJS_Logic;
--component¸¦ È£ÃâÇÏ´Â entity
library ieee;
use ieee.std_logic_1164.all;
entity FA is
port(w, x, y : in std_logic;
carry, sum : out std_logic);
end FA;
architecture JMJS_Logic of FA is
signal temp_c1, temp_c2, temp_s : std_logic;
component HA
port(x, y : in std_logic;
c, s : out std_logic);
end component;
component or2
port(a, b : in std_logic;
c : out std_logic);
end component;
begin
u1 : HA port map(w, x, temp_c1, temp_s);
u2 : HA port map(temp_s, y, temp_c2, sum);
u3 : or2 port map(temp_c1, temp_c2, carry);
end JMJS_Logic; |
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