`timescale 1 ns / 100 ps module abc (); reg clk; initial clk=1; always #5 clk=~clk; reg [3:0] count; initial count=0; always @(posedge clk) count<=count+1; always @(negedge clk) $strobe("count=%d",count); wire [2:0] cflag = (count[1])? (count[0])? 0:1 : (count[0])? 2:3; initial forever #7 $display("%0.2fms count=%d cflag=%d",$realtime/100,count,cflag); initial begin $dumpfile("abc.vcd"); $dumpvars; #1000 $finish; end endmodule