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Edge Detecter
# 12 Jamie    02.8.29 13:16

1.Spec

Edge Detector를 설계해 보겠습니다.
여기에는 상승 edge detector와 하강 edge detector가 있습니다.
Data의 상승 또는 하강이 있으면 클럭 한 주기의 로직 '1'을 발생합니다.
어떤식으로 상승, 하강 edge를 check하는지 source를 분석해 봅시다.
data1이 data의 이전 값을 가지고 있는 것이 source를 이해하기위한 key point입니다.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : rising_edge_detector.vhd
  falling_edge_detector.vhd
  Test Vector : riding_edge_detector_tb.vhd
  falling_edge_detector_tb.vhd
게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
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92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2000
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87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6128
86  ncverilog option example JMJS 10.6.8 7540
85  [Verilog]Latch example JMJS 08.12.1 2419
84  Pad verilog example JMJS 01.3.16 4322
83  [ModelSim] vector JMJS 01.3.16 2018
82  RTL Code 분석순서 JMJS 09.4.29 2315
81  [temp]PIPE JMJS 08.10.2 1679
80  [temp]always-forever 무한루프 JMJS 08.10.2 1771
79  YCbCr2RGB.v JMJS 10.5.12 1967
78  [VHDL]rom64x8 JMJS 09.3.27 1573
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76  [function]vector2integer JMJS 02.6.19 1611
75  [VHDL]ram8x4x8 JMJS 08.12.1 1493
74  [예]shift JMJS 02.6.19 1841
73  test JMJS 09.7.20 1627
72  test JMJS 09.7.20 1431
71  test JMJS 09.7.20 1364
70  test JMJS 09.7.20 1474
69  test JMJS 09.7.20 1496
68  test JMJS 09.7.20 1418
67  test JMJS 09.7.20 1343
66  test JMJS 09.7.20 1304
65  test JMJS 09.7.20 1411
64  test JMJS 09.7.20 1668
63  test JMJS 09.7.20 1658
62  test JMJS 09.7.20 1589
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3371
60  test JMJS 09.7.20 1356
59  test JMJS 09.7.20 1435
58  test JMJS 09.7.20 1445
57  test JMJS 09.7.20 1380
56  test JMJS 09.7.20 1431
55  verilog 학과 샘플강의 JMJS 16.5.30 2050
54  [verilog]create_generated_clock JMJS 15.4.28 2013
53  [Verilog]JDIFF JMJS 14.7.4 1296
52  [verilog]parameter definition JMJS 14.3.5 1563
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4513
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2280
49  Verdi JMJS 10.4.22 2876
48  draw hexa JMJS 10.4.9 1634
47  asfifo - Async FIFO JMJS 10.4.8 1468
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45  synplify batch JMJS 10.3.8 2224
44  전자시계 Type A JMJS 08.11.28 1720
43  I2C Webpage JMJS 08.2.25 1586
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5725
41  [Verilog]vstring JMJS 17.9.27 1820
40  Riviera Simple Case JMJS 09.4.29 2962
39  [VHDL]DES Example JMJS 07.6.15 2705
38  [verilog]RAM example JMJS 09.6.5 2481
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1745
36  Jamie's VHDL Handbook JMJS 08.11.28 2401
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33  [VHDL]type example - package TYPES JMJS 06.2.2 1560
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8  Concept2 Jamie 02.8.28 1756
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1  Two Input Logic Jamie 02.8.26 2204
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