LogIn E-mail
설계이야기
사과장수이야기 
Study-HDL 
Script Tip 
Perl Tip 
C Memo 
Python Memo 
Edge Detecter
# 12 Jamie    02.8.29 13:16

1.Spec

Edge Detector를 설계해 보겠습니다.
여기에는 상승 edge detector와 하강 edge detector가 있습니다.
Data의 상승 또는 하강이 있으면 클럭 한 주기의 로직 '1'을 발생합니다.
어떤식으로 상승, 하강 edge를 check하는지 source를 분석해 봅시다.
data1이 data의 이전 값을 가지고 있는 것이 source를 이해하기위한 key point입니다.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : rising_edge_detector.vhd
  falling_edge_detector.vhd
  Test Vector : riding_edge_detector_tb.vhd
  falling_edge_detector_tb.vhd
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 313
97  test plusargs value plusargs JMJS 24.9.5 340
96  color text JMJS 24.7.13 372
95  draw_hexa.v JMJS 10.6.17 2534
94  jmjsxram3.v JMJS 10.4.9 2401
93  Verilog document JMJS 11.1.24 3000
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2589
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4022
90  gtkwave PC version JMJS 09.3.30 2385
89  ncsim option example JMJS 08.12.1 4761
88  [영상]keywords for web search JMJS 08.12.1 2364
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6539
86  ncverilog option example JMJS 10.6.8 8218
85  [Verilog]Latch example JMJS 08.12.1 2962
84  Pad verilog example JMJS 01.3.16 4894
83  [ModelSim] vector JMJS 01.3.16 2580
82  RTL Code 분석순서 JMJS 09.4.29 2838
81  [temp]PIPE JMJS 08.10.2 2232
80  [temp]always-forever 무한루프 JMJS 08.10.2 2304
79  YCbCr2RGB.v JMJS 10.5.12 2503
78  [VHDL]rom64x8 JMJS 09.3.27 2061
77  [function]vector_compare JMJS 02.6.19 1962
76  [function]vector2integer JMJS 02.6.19 2155
75  [VHDL]ram8x4x8 JMJS 08.12.1 1909
74  [예]shift JMJS 02.6.19 2350
73  test JMJS 09.7.20 2187
72  test JMJS 09.7.20 1784
71  test JMJS 09.7.20 1903
70  test JMJS 09.7.20 1999
69  test JMJS 09.7.20 2042
68  test JMJS 09.7.20 1974
67  test JMJS 09.7.20 1910
66  test JMJS 09.7.20 1863
65  test JMJS 09.7.20 1975
64  test JMJS 09.7.20 2177
63  test JMJS 09.7.20 2209
62  test JMJS 09.7.20 2107
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3896
60  test JMJS 09.7.20 1719
59  test JMJS 09.7.20 2018
58  test JMJS 09.7.20 1935
57  test JMJS 09.7.20 1903
56  test JMJS 09.7.20 1946
55  verilog 학과 샘플강의 JMJS 16.5.30 2425
54  [verilog]create_generated_clock JMJS 15.4.28 2404
53  [Verilog]JDIFF JMJS 14.7.4 1770
52  [verilog]parameter definition JMJS 14.3.5 2051
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4992
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2675
49  Verdi JMJS 10.4.22 3534
48  draw hexa JMJS 10.4.9 2057
47  asfifo - Async FIFO JMJS 10.4.8 1917
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3586
45  synplify batch JMJS 10.3.8 2764
44  전자시계 Type A JMJS 08.11.28 2268
43  I2C Webpage JMJS 08.2.25 2100
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6231
41  [Verilog]vstring JMJS 17.9.27 2311
40  Riviera Simple Case JMJS 09.4.29 3407
39  [VHDL]DES Example JMJS 07.6.15 3257
38  [verilog]RAM example JMJS 09.6.5 3035
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2269
36  Jamie's VHDL Handbook JMJS 08.11.28 2953
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3540
34  RTL Job JMJS 09.4.29 2461
33  [VHDL]type example - package TYPES JMJS 06.2.2 1961
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9609
30  [verilog]array_module JMJS 05.12.8 2512
29  [verilog-2001]generate JMJS 05.12.8 3657
28  protected JMJS 05.11.18 2306
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3071
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2059
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2681
23  Array Of Array JMJS 04.8.16 2206
22  dumpfile, dumpvars JMJS 04.7.19 3892
21  Vending Machine Jamie 02.12.16 10326
20  Mini Vending Machine1 Jamie 02.12.10 7204
19  Mini Vending Machine Jamie 02.12.6 10042
18  Key Jamie 02.11.29 5224
17  Stop Watch Jamie 02.11.25 5805
16  Mealy Machine Jamie 02.8.29 6962
15  Moore Machine Jamie 02.8.29 18298
14  Up Down Counter Jamie 02.8.29 4321
13  Up Counter Jamie 02.8.29 3021
12  Edge Detecter Jamie 02.8.29 3230
11  Concept4 Jamie 02.8.28 2226
10  Concept3 Jamie 02.8.28 2300
9  Concept2_1 Jamie 02.8.28 2190
8  Concept2 Jamie 02.8.28 2281
7  Concept1 Jamie 02.8.26 2350
6  Tri State Buffer Jamie 02.8.26 3856
5  8x3 Encoder Jamie 02.8.28 4431
4  3x8 Decoder Jamie 02.8.28 4064
3  4bit Comparator Jamie 02.8.26 3446
2  가위 바위 보 게임 Jamie 02.8.26 5644
1  Two Input Logic Jamie 02.8.26 2694
[1]