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# 46 JMJS    02.3.14 21:24

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98  interface JMJS 25.1.20 345
97  test plusargs value plusargs JMJS 24.9.5 355
96  color text JMJS 24.7.13 408
95  draw_hexa.v JMJS 10.6.17 2555
94  jmjsxram3.v JMJS 10.4.9 2508
93  Verilog document JMJS 11.1.24 3088
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2692
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4131
90  gtkwave PC version JMJS 09.3.30 2523
89  ncsim option example JMJS 08.12.1 4871
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2470
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6561
86  ncverilog option example JMJS 10.6.8 8330
85  [Verilog]Latch example JMJS 08.12.1 3058
84  Pad verilog example JMJS 01.3.16 5007
83  [ModelSim] vector JMJS 01.3.16 2690
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2940
81  [temp]PIPE JMJS 08.10.2 2344
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2425
79  YCbCr2RGB.v JMJS 10.5.12 2587
78  [VHDL]rom64x8 JMJS 09.3.27 2140
77  [function]vector_compare JMJS 02.6.19 2007
76  [function]vector2integer JMJS 02.6.19 2265
75  [VHDL]ram8x4x8 JMJS 08.12.1 1961
74  [¿¹]shift JMJS 02.6.19 2440
73  test JMJS 09.7.20 2298
72  test JMJS 09.7.20 1801
71  test JMJS 09.7.20 2029
70  test JMJS 09.7.20 2100
69  test JMJS 09.7.20 2151
68  test JMJS 09.7.20 2100
67  test JMJS 09.7.20 2037
66  test JMJS 09.7.20 1979
65  test JMJS 09.7.20 2097
64  test JMJS 09.7.20 2277
63  test JMJS 09.7.20 2330
62  test JMJS 09.7.20 2205
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3989
60  test JMJS 09.7.20 1732
59  test JMJS 09.7.20 2138
58  test JMJS 09.7.20 2052
57  test JMJS 09.7.20 2009
56  test JMJS 09.7.20 2058
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2442
54  [verilog]create_generated_clock JMJS 15.4.28 2436
53  [Verilog]JDIFF JMJS 14.7.4 1892
52  [verilog]parameter definition JMJS 14.3.5 2163
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5109
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2709
49  Verdi JMJS 10.4.22 3644
48  draw hexa JMJS 10.4.9 2101
47  asfifo - Async FIFO JMJS 10.4.8 1965
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3662
45  synplify batch JMJS 10.3.8 2867
44  ÀüÀڽðè Type A JMJS 08.11.28 2388
43  I2C Webpage JMJS 08.2.25 2203
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6256
41  [Verilog]vstring JMJS 17.9.27 2384
40  Riviera Simple Case JMJS 09.4.29 3473
39  [VHDL]DES Example JMJS 07.6.15 3368
38  [verilog]RAM example JMJS 09.6.5 3140
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2375
36  Jamie's VHDL Handbook JMJS 08.11.28 3059
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3657
34  RTL Job JMJS 09.4.29 2585
33  [VHDL]type example - package TYPES JMJS 06.2.2 1992
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9701
30  [verilog]array_module JMJS 05.12.8 2602
29  [verilog-2001]generate JMJS 05.12.8 3753
28  protected JMJS 05.11.18 2428
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3135
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2101
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2744
23  Array Of Array JMJS 04.8.16 2288
22  dumpfile, dumpvars JMJS 04.7.19 3996
21  Vending Machine Jamie 02.12.16 10428
20  Mini Vending Machine1 Jamie 02.12.10 7292
19  Mini Vending Machine Jamie 02.12.6 10115
18  Key Jamie 02.11.29 5329
17  Stop Watch Jamie 02.11.25 5835
16  Mealy Machine Jamie 02.8.29 7051
15  Moore Machine Jamie 02.8.29 18388
14  Up Down Counter Jamie 02.8.29 4438
13  Up Counter Jamie 02.8.29 3134
12  Edge Detecter Jamie 02.8.29 3329
11  Concept4 Jamie 02.8.28 2246
10  Concept3 Jamie 02.8.28 2391
9  Concept2_1 Jamie 02.8.28 2275
8  Concept2 Jamie 02.8.28 2362
7  Concept1 Jamie 02.8.26 2363
6  Tri State Buffer Jamie 02.8.26 3979
5  8x3 Encoder Jamie 02.8.28 4530
4  3x8 Decoder Jamie 02.8.28 4157
3  4bit Comparator Jamie 02.8.26 3548
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5657
1  Two Input Logic Jamie 02.8.26 2800
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