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VHDL을 이용한 회로설계의 장점
# 46 JMJS    02.3.14 21:24

① EDA S/W나 ASIC Library에 구애 받지 않고 회로를 설계할 수가 있습니다.

② Gate의 Timing 정보와 동작 상태 뿐만 아니라 반도체 내부 회로의
   Design Block,   나아가 System 설계까지 가능합니다.

③ Synthesis Tool을 이용하여 검증된 실제 반도체 설계회로를 얻을 수 있습니다.

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2183
94  jmjsxram3.v JMJS 10.4.9 1915
93  Verilog document JMJS 11.1.24 2500
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2054
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3526
90  gtkwave PC version JMJS 09.3.30 1864
89  ncsim option example JMJS 08.12.1 4233
88  [영상]keywords for web search JMJS 08.12.1 1867
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6188
86  ncverilog option example JMJS 10.6.8 7615
85  [Verilog]Latch example JMJS 08.12.1 2472
84  Pad verilog example JMJS 01.3.16 4385
83  [ModelSim] vector JMJS 01.3.16 2074
82  RTL Code 분석순서 JMJS 09.4.29 2370
81  [temp]PIPE JMJS 08.10.2 1737
80  [temp]always-forever 무한루프 JMJS 08.10.2 1824
79  YCbCr2RGB.v JMJS 10.5.12 2020
78  [VHDL]rom64x8 JMJS 09.3.27 1626
77  [function]vector_compare JMJS 02.6.19 1592
76  [function]vector2integer JMJS 02.6.19 1663
75  [VHDL]ram8x4x8 JMJS 08.12.1 1548
74  [예]shift JMJS 02.6.19 1892
73  test JMJS 09.7.20 1691
72  test JMJS 09.7.20 1484
71  test JMJS 09.7.20 1418
70  test JMJS 09.7.20 1523
69  test JMJS 09.7.20 1553
68  test JMJS 09.7.20 1476
67  test JMJS 09.7.20 1405
66  test JMJS 09.7.20 1357
65  test JMJS 09.7.20 1473
64  test JMJS 09.7.20 1719
63  test JMJS 09.7.20 1712
62  test JMJS 09.7.20 1639
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3425
60  test JMJS 09.7.20 1415
59  test JMJS 09.7.20 1495
58  test JMJS 09.7.20 1492
57  test JMJS 09.7.20 1433
56  test JMJS 09.7.20 1478
55  verilog 학과 샘플강의 JMJS 16.5.30 2097
54  [verilog]create_generated_clock JMJS 15.4.28 2070
53  [Verilog]JDIFF JMJS 14.7.4 1348
52  [verilog]parameter definition JMJS 14.3.5 1612
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4569
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2333
49  Verdi JMJS 10.4.22 2959
48  draw hexa JMJS 10.4.9 1688
47  asfifo - Async FIFO JMJS 10.4.8 1516
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3157
45  synplify batch JMJS 10.3.8 2273
44  전자시계 Type A JMJS 08.11.28 1777
43  I2C Webpage JMJS 08.2.25 1633
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5780
41  [Verilog]vstring JMJS 17.9.27 1864
40  Riviera Simple Case JMJS 09.4.29 3007
39  [VHDL]DES Example JMJS 07.6.15 2754
38  [verilog]RAM example JMJS 09.6.5 2531
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1796
36  Jamie's VHDL Handbook JMJS 08.11.28 2455
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3090
34  RTL Job JMJS 09.4.29 1932
33  [VHDL]type example - package TYPES JMJS 06.2.2 1615
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9140
30  [verilog]array_module JMJS 05.12.8 2046
29  [verilog-2001]generate JMJS 05.12.8 3177
28  protected JMJS 05.11.18 1829
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2636
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1696
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2259
23  Array Of Array JMJS 04.8.16 1787
22  dumpfile, dumpvars JMJS 04.7.19 3407
21  Vending Machine Jamie 02.12.16 9869
20  Mini Vending Machine1 Jamie 02.12.10 6706
19  Mini Vending Machine Jamie 02.12.6 9524
18  Key Jamie 02.11.29 4763
17  Stop Watch Jamie 02.11.25 5486
16  Mealy Machine Jamie 02.8.29 6519
15  Moore Machine Jamie 02.8.29 17623
14  Up Down Counter Jamie 02.8.29 3826
13  Up Counter Jamie 02.8.29 2562
12  Edge Detecter Jamie 02.8.29 2752
11  Concept4 Jamie 02.8.28 1902
10  Concept3 Jamie 02.8.28 1853
9  Concept2_1 Jamie 02.8.28 1737
8  Concept2 Jamie 02.8.28 1809
7  Concept1 Jamie 02.8.26 2015
6  Tri State Buffer Jamie 02.8.26 3323
5  8x3 Encoder Jamie 02.8.28 3919
4  3x8 Decoder Jamie 02.8.28 3589
3  4bit Comparator Jamie 02.8.26 2988
2  가위 바위 보 게임 Jamie 02.8.26 5340
1  Two Input Logic Jamie 02.8.26 2256
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