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[verilog]array_module
# 30 JMJS    05.12.8 09:09

module array_module (clk, rst, in_data, out_data);

  parameter Depth = 17;
  parameter Width = 64;

  input              clk;
  input              rst;
  input  [Width-1:0] in_data;
  output [Width-1:0] out_data;

  reg         [Depth-1:0] addr;
  reg    [Width-1:0] MemCore [0:2^Depth-1];

  always @(posedge clk or negedge rst) begin
    if (~rst) begin
            addr <= 0;
    end
    else begin
                MemCore[addr] <= in_data;
            addr <= addr + 1;
    end
  end

  assign out_data = MemCore[addr];

endmodule

module tb_array_module ();

  parameter Depth = 17;
  parameter Width = 64;
  parameter HalfClock = 20;

  reg                clk;
  reg                rst;
  reg                wr_en;
  reg    [Depth-1:0] addr;
  reg    [Width-1:0] in_data;
  wire   [Width-1:0] out_data;

  always begin
    clk <= 1'b0;
    #HalfClock;
    clk <= 1'b1;
    #HalfClock;
  end

  initial begin
    Initial;
    Memory_Write;
    Memory_Read;
    $stop;
  end

task Initial;
  begin
    rst            = 1'b1;
    wr_en   = 1'b0;
    in_data = 64'h0;
    addr    = 17'h0;
    #1000;
    rst     = 1'b0;
    #1000;
    rst     = 1'b1;
    #1000;
  end
endtask

task Memory_Write;
integer i;
  begin
    @(negedge clk);
    wr_en = 1'b1;
    for (i=0; i<2^Depth; i=i+1) begin
      addr    = i;
      in_data = i;
      @(negedge clk);
    end
    wr_en = 1'b0;
    repeat(5) @(negedge clk);
  end
endtask

task Memory_Read;
integer i;
  begin
    @(posedge clk);
    for (i=0; i<2^Depth; i=i+1) begin
      addr   = i;
      @(posedge clk);
    end
    repeat(5) @(posedge clk);
  end
endtask

array_module array_module (clk, rst, in_data, out_data);

endmodule

게시물: 93 건, 현재: 1 / 1 쪽
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