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test
# 69 JMJS    09.7.20 15:57

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 269
97  test plusargs value plusargs JMJS 24.9.5 312
96  color text JMJS 24.7.13 330
95  draw_hexa.v JMJS 10.6.17 2515
94  jmjsxram3.v JMJS 10.4.9 2310
93  Verilog document JMJS 11.1.24 2915
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2499
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3920
90  gtkwave PC version JMJS 09.3.30 2285
89  ncsim option example JMJS 08.12.1 4653
88  [영상]keywords for web search JMJS 08.12.1 2282
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6506
86  ncverilog option example JMJS 10.6.8 8117
85  [Verilog]Latch example JMJS 08.12.1 2863
84  Pad verilog example JMJS 01.3.16 4783
83  [ModelSim] vector JMJS 01.3.16 2476
82  RTL Code 분석순서 JMJS 09.4.29 2744
81  [temp]PIPE JMJS 08.10.2 2132
80  [temp]always-forever 무한루프 JMJS 08.10.2 2217
79  YCbCr2RGB.v JMJS 10.5.12 2407
78  [VHDL]rom64x8 JMJS 09.3.27 1987
77  [function]vector_compare JMJS 02.6.19 1889
76  [function]vector2integer JMJS 02.6.19 2049
75  [VHDL]ram8x4x8 JMJS 08.12.1 1864
74  [예]shift JMJS 02.6.19 2280
73  test JMJS 09.7.20 2084
72  test JMJS 09.7.20 1767
71  test JMJS 09.7.20 1797
70  test JMJS 09.7.20 1897
69  test JMJS 09.7.20 1938
68  test JMJS 09.7.20 1870
67  test JMJS 09.7.20 1805
66  test JMJS 09.7.20 1777
65  test JMJS 09.7.20 1877
64  test JMJS 09.7.20 2078
63  test JMJS 09.7.20 2099
62  test JMJS 09.7.20 2024
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3821
60  test JMJS 09.7.20 1699
59  test JMJS 09.7.20 1888
58  test JMJS 09.7.20 1858
57  test JMJS 09.7.20 1821
56  test JMJS 09.7.20 1865
55  verilog 학과 샘플강의 JMJS 16.5.30 2389
54  [verilog]create_generated_clock JMJS 15.4.28 2368
53  [Verilog]JDIFF JMJS 14.7.4 1667
52  [verilog]parameter definition JMJS 14.3.5 1965
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4916
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2635
49  Verdi JMJS 10.4.22 3432
48  draw hexa JMJS 10.4.9 2003
47  asfifo - Async FIFO JMJS 10.4.8 1872
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3523
45  synplify batch JMJS 10.3.8 2659
44  전자시계 Type A JMJS 08.11.28 2170
43  I2C Webpage JMJS 08.2.25 2001
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6161
41  [Verilog]vstring JMJS 17.9.27 2227
40  Riviera Simple Case JMJS 09.4.29 3341
39  [VHDL]DES Example JMJS 07.6.15 3159
38  [verilog]RAM example JMJS 09.6.5 2920
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2195
36  Jamie's VHDL Handbook JMJS 08.11.28 2855
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3474
34  RTL Job JMJS 09.4.29 2328
33  [VHDL]type example - package TYPES JMJS 06.2.2 1922
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9525
30  [verilog]array_module JMJS 05.12.8 2435
29  [verilog-2001]generate JMJS 05.12.8 3551
28  protected JMJS 05.11.18 2221
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2998
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1980
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2630
23  Array Of Array JMJS 04.8.16 2146
22  dumpfile, dumpvars JMJS 04.7.19 3784
21  Vending Machine Jamie 02.12.16 10235
20  Mini Vending Machine1 Jamie 02.12.10 7116
19  Mini Vending Machine Jamie 02.12.6 9967
18  Key Jamie 02.11.29 5134
17  Stop Watch Jamie 02.11.25 5761
16  Mealy Machine Jamie 02.8.29 6887
15  Moore Machine Jamie 02.8.29 18203
14  Up Down Counter Jamie 02.8.29 4230
13  Up Counter Jamie 02.8.29 2917
12  Edge Detecter Jamie 02.8.29 3144
11  Concept4 Jamie 02.8.28 2194
10  Concept3 Jamie 02.8.28 2228
9  Concept2_1 Jamie 02.8.28 2109
8  Concept2 Jamie 02.8.28 2207
7  Concept1 Jamie 02.8.26 2334
6  Tri State Buffer Jamie 02.8.26 3737
5  8x3 Encoder Jamie 02.8.28 4342
4  3x8 Decoder Jamie 02.8.28 3988
3  4bit Comparator Jamie 02.8.26 3365
2  가위 바위 보 게임 Jamie 02.8.26 5623
1  Two Input Logic Jamie 02.8.26 2599
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