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test
# 69 JMJS    09.7.20 15:57

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 335
97  test plusargs value plusargs JMJS 24.9.5 349
96  color text JMJS 24.7.13 389
95  draw_hexa.v JMJS 10.6.17 2544
94  jmjsxram3.v JMJS 10.4.9 2452
93  Verilog document JMJS 11.1.24 3053
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2640
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4076
90  gtkwave PC version JMJS 09.3.30 2447
89  ncsim option example JMJS 08.12.1 4807
88  [영상]keywords for web search JMJS 08.12.1 2411
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6548
86  ncverilog option example JMJS 10.6.8 8271
85  [Verilog]Latch example JMJS 08.12.1 3007
84  Pad verilog example JMJS 01.3.16 4950
83  [ModelSim] vector JMJS 01.3.16 2637
82  RTL Code 분석순서 JMJS 09.4.29 2873
81  [temp]PIPE JMJS 08.10.2 2279
80  [temp]always-forever 무한루프 JMJS 08.10.2 2354
79  YCbCr2RGB.v JMJS 10.5.12 2547
78  [VHDL]rom64x8 JMJS 09.3.27 2105
77  [function]vector_compare JMJS 02.6.19 1992
76  [function]vector2integer JMJS 02.6.19 2207
75  [VHDL]ram8x4x8 JMJS 08.12.1 1929
74  [예]shift JMJS 02.6.19 2393
73  test JMJS 09.7.20 2243
72  test JMJS 09.7.20 1792
71  test JMJS 09.7.20 1959
70  test JMJS 09.7.20 2047
69  test JMJS 09.7.20 2096
68  test JMJS 09.7.20 2036
67  test JMJS 09.7.20 1967
66  test JMJS 09.7.20 1913
65  test JMJS 09.7.20 2037
64  test JMJS 09.7.20 2226
63  test JMJS 09.7.20 2267
62  test JMJS 09.7.20 2157
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3942
60  test JMJS 09.7.20 1725
59  test JMJS 09.7.20 2086
58  test JMJS 09.7.20 1989
57  test JMJS 09.7.20 1956
56  test JMJS 09.7.20 1993
55  verilog 학과 샘플강의 JMJS 16.5.30 2433
54  [verilog]create_generated_clock JMJS 15.4.28 2418
53  [Verilog]JDIFF JMJS 14.7.4 1830
52  [verilog]parameter definition JMJS 14.3.5 2106
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5045
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2693
49  Verdi JMJS 10.4.22 3592
48  draw hexa JMJS 10.4.9 2084
47  asfifo - Async FIFO JMJS 10.4.8 1942
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3624
45  synplify batch JMJS 10.3.8 2823
44  전자시계 Type A JMJS 08.11.28 2315
43  I2C Webpage JMJS 08.2.25 2147
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6244
41  [Verilog]vstring JMJS 17.9.27 2357
40  Riviera Simple Case JMJS 09.4.29 3441
39  [VHDL]DES Example JMJS 07.6.15 3310
38  [verilog]RAM example JMJS 09.6.5 3076
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2321
36  Jamie's VHDL Handbook JMJS 08.11.28 3016
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3593
34  RTL Job JMJS 09.4.29 2530
33  [VHDL]type example - package TYPES JMJS 06.2.2 1975
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9656
30  [verilog]array_module JMJS 05.12.8 2562
29  [verilog-2001]generate JMJS 05.12.8 3702
28  protected JMJS 05.11.18 2365
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3096
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2084
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2714
23  Array Of Array JMJS 04.8.16 2247
22  dumpfile, dumpvars JMJS 04.7.19 3949
21  Vending Machine Jamie 02.12.16 10382
20  Mini Vending Machine1 Jamie 02.12.10 7239
19  Mini Vending Machine Jamie 02.12.6 10076
18  Key Jamie 02.11.29 5289
17  Stop Watch Jamie 02.11.25 5819
16  Mealy Machine Jamie 02.8.29 7004
15  Moore Machine Jamie 02.8.29 18346
14  Up Down Counter Jamie 02.8.29 4369
13  Up Counter Jamie 02.8.29 3061
12  Edge Detecter Jamie 02.8.29 3284
11  Concept4 Jamie 02.8.28 2235
10  Concept3 Jamie 02.8.28 2345
9  Concept2_1 Jamie 02.8.28 2236
8  Concept2 Jamie 02.8.28 2325
7  Concept1 Jamie 02.8.26 2356
6  Tri State Buffer Jamie 02.8.26 3928
5  8x3 Encoder Jamie 02.8.28 4474
4  3x8 Decoder Jamie 02.8.28 4114
3  4bit Comparator Jamie 02.8.26 3484
2  가위 바위 보 게임 Jamie 02.8.26 5649
1  Two Input Logic Jamie 02.8.26 2742
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