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test
# 69 JMJS    09.7.20 15:57

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 300
97  test plusargs value plusargs JMJS 24.9.5 336
96  color text JMJS 24.7.13 362
95  draw_hexa.v JMJS 10.6.17 2530
94  jmjsxram3.v JMJS 10.4.9 2379
93  Verilog document JMJS 11.1.24 2983
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2561
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3987
90  gtkwave PC version JMJS 09.3.30 2359
89  ncsim option example JMJS 08.12.1 4730
88  [영상]keywords for web search JMJS 08.12.1 2330
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6534
86  ncverilog option example JMJS 10.6.8 8186
85  [Verilog]Latch example JMJS 08.12.1 2927
84  Pad verilog example JMJS 01.3.16 4873
83  [ModelSim] vector JMJS 01.3.16 2543
82  RTL Code 분석순서 JMJS 09.4.29 2814
81  [temp]PIPE JMJS 08.10.2 2201
80  [temp]always-forever 무한루프 JMJS 08.10.2 2282
79  YCbCr2RGB.v JMJS 10.5.12 2474
78  [VHDL]rom64x8 JMJS 09.3.27 2040
77  [function]vector_compare JMJS 02.6.19 1942
76  [function]vector2integer JMJS 02.6.19 2124
75  [VHDL]ram8x4x8 JMJS 08.12.1 1900
74  [예]shift JMJS 02.6.19 2326
73  test JMJS 09.7.20 2156
72  test JMJS 09.7.20 1780
71  test JMJS 09.7.20 1876
70  test JMJS 09.7.20 1970
69  test JMJS 09.7.20 2015
68  test JMJS 09.7.20 1948
67  test JMJS 09.7.20 1884
66  test JMJS 09.7.20 1835
65  test JMJS 09.7.20 1940
64  test JMJS 09.7.20 2145
63  test JMJS 09.7.20 2178
62  test JMJS 09.7.20 2089
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3872
60  test JMJS 09.7.20 1718
59  test JMJS 09.7.20 1983
58  test JMJS 09.7.20 1916
57  test JMJS 09.7.20 1879
56  test JMJS 09.7.20 1923
55  verilog 학과 샘플강의 JMJS 16.5.30 2421
54  [verilog]create_generated_clock JMJS 15.4.28 2393
53  [Verilog]JDIFF JMJS 14.7.4 1733
52  [verilog]parameter definition JMJS 14.3.5 2030
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4962
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2664
49  Verdi JMJS 10.4.22 3498
48  draw hexa JMJS 10.4.9 2037
47  asfifo - Async FIFO JMJS 10.4.8 1904
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3578
45  synplify batch JMJS 10.3.8 2732
44  전자시계 Type A JMJS 08.11.28 2241
43  I2C Webpage JMJS 08.2.25 2079
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6218
41  [Verilog]vstring JMJS 17.9.27 2292
40  Riviera Simple Case JMJS 09.4.29 3380
39  [VHDL]DES Example JMJS 07.6.15 3226
38  [verilog]RAM example JMJS 09.6.5 3001
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2253
36  Jamie's VHDL Handbook JMJS 08.11.28 2916
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3519
34  RTL Job JMJS 09.4.29 2427
33  [VHDL]type example - package TYPES JMJS 06.2.2 1954
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9588
30  [verilog]array_module JMJS 05.12.8 2483
29  [verilog-2001]generate JMJS 05.12.8 3619
28  protected JMJS 05.11.18 2278
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3049
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2047
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2663
23  Array Of Array JMJS 04.8.16 2187
22  dumpfile, dumpvars JMJS 04.7.19 3859
21  Vending Machine Jamie 02.12.16 10298
20  Mini Vending Machine1 Jamie 02.12.10 7176
19  Mini Vending Machine Jamie 02.12.6 10022
18  Key Jamie 02.11.29 5195
17  Stop Watch Jamie 02.11.25 5797
16  Mealy Machine Jamie 02.8.29 6939
15  Moore Machine Jamie 02.8.29 18277
14  Up Down Counter Jamie 02.8.29 4294
13  Up Counter Jamie 02.8.29 2990
12  Edge Detecter Jamie 02.8.29 3207
11  Concept4 Jamie 02.8.28 2217
10  Concept3 Jamie 02.8.28 2280
9  Concept2_1 Jamie 02.8.28 2169
8  Concept2 Jamie 02.8.28 2259
7  Concept1 Jamie 02.8.26 2346
6  Tri State Buffer Jamie 02.8.26 3818
5  8x3 Encoder Jamie 02.8.28 4414
4  3x8 Decoder Jamie 02.8.28 4039
3  4bit Comparator Jamie 02.8.26 3429
2  가위 바위 보 게임 Jamie 02.8.26 5642
1  Two Input Logic Jamie 02.8.26 2670
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