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test
# 69 JMJS    09.7.20 15:57

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 358
97  test plusargs value plusargs JMJS 24.9.5 366
96  color text JMJS 24.7.13 419
95  draw_hexa.v JMJS 10.6.17 2568
94  jmjsxram3.v JMJS 10.4.9 2559
93  Verilog document JMJS 11.1.24 3123
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2733
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4158
90  gtkwave PC version JMJS 09.3.30 2540
89  ncsim option example JMJS 08.12.1 4891
88  [영상]keywords for web search JMJS 08.12.1 2492
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6578
86  ncverilog option example JMJS 10.6.8 8366
85  [Verilog]Latch example JMJS 08.12.1 3094
84  Pad verilog example JMJS 01.3.16 5044
83  [ModelSim] vector JMJS 01.3.16 2714
82  RTL Code 분석순서 JMJS 09.4.29 2964
81  [temp]PIPE JMJS 08.10.2 2375
80  [temp]always-forever 무한루프 JMJS 08.10.2 2465
79  YCbCr2RGB.v JMJS 10.5.12 2601
78  [VHDL]rom64x8 JMJS 09.3.27 2176
77  [function]vector_compare JMJS 02.6.19 2022
76  [function]vector2integer JMJS 02.6.19 2302
75  [VHDL]ram8x4x8 JMJS 08.12.1 1987
74  [예]shift JMJS 02.6.19 2457
73  test JMJS 09.7.20 2337
72  test JMJS 09.7.20 1812
71  test JMJS 09.7.20 2066
70  test JMJS 09.7.20 2149
69  test JMJS 09.7.20 2185
68  test JMJS 09.7.20 2129
67  test JMJS 09.7.20 2070
66  test JMJS 09.7.20 2034
65  test JMJS 09.7.20 2144
64  test JMJS 09.7.20 2302
63  test JMJS 09.7.20 2363
62  test JMJS 09.7.20 2258
61  VHDL의 연산자 우선순위 JMJS 09.7.20 4047
60  test JMJS 09.7.20 1744
59  test JMJS 09.7.20 2191
58  test JMJS 09.7.20 2105
57  test JMJS 09.7.20 2049
56  test JMJS 09.7.20 2111
55  verilog 학과 샘플강의 JMJS 16.5.30 2457
54  [verilog]create_generated_clock JMJS 15.4.28 2449
53  [Verilog]JDIFF JMJS 14.7.4 1926
52  [verilog]parameter definition JMJS 14.3.5 2201
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5157
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2721
49  Verdi JMJS 10.4.22 3658
48  draw hexa JMJS 10.4.9 2109
47  asfifo - Async FIFO JMJS 10.4.8 1981
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3684
45  synplify batch JMJS 10.3.8 2891
44  전자시계 Type A JMJS 08.11.28 2428
43  I2C Webpage JMJS 08.2.25 2253
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6267
41  [Verilog]vstring JMJS 17.9.27 2409
40  Riviera Simple Case JMJS 09.4.29 3509
39  [VHDL]DES Example JMJS 07.6.15 3419
38  [verilog]RAM example JMJS 09.6.5 3195
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2427
36  Jamie's VHDL Handbook JMJS 08.11.28 3084
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3691
34  RTL Job JMJS 09.4.29 2618
33  [VHDL]type example - package TYPES JMJS 06.2.2 2008
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9728
30  [verilog]array_module JMJS 05.12.8 2643
29  [verilog-2001]generate JMJS 05.12.8 3790
28  protected JMJS 05.11.18 2485
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3160
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2114
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2786
23  Array Of Array JMJS 04.8.16 2323
22  dumpfile, dumpvars JMJS 04.7.19 4033
21  Vending Machine Jamie 02.12.16 10462
20  Mini Vending Machine1 Jamie 02.12.10 7351
19  Mini Vending Machine Jamie 02.12.6 10135
18  Key Jamie 02.11.29 5365
17  Stop Watch Jamie 02.11.25 5849
16  Mealy Machine Jamie 02.8.29 7078
15  Moore Machine Jamie 02.8.29 18426
14  Up Down Counter Jamie 02.8.29 4489
13  Up Counter Jamie 02.8.29 3172
12  Edge Detecter Jamie 02.8.29 3367
11  Concept4 Jamie 02.8.28 2258
10  Concept3 Jamie 02.8.28 2427
9  Concept2_1 Jamie 02.8.28 2298
8  Concept2 Jamie 02.8.28 2374
7  Concept1 Jamie 02.8.26 2374
6  Tri State Buffer Jamie 02.8.26 4018
5  8x3 Encoder Jamie 02.8.28 4585
4  3x8 Decoder Jamie 02.8.28 4213
3  4bit Comparator Jamie 02.8.26 3590
2  가위 바위 보 게임 Jamie 02.8.26 5671
1  Two Input Logic Jamie 02.8.26 2836
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