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전자시계 Type A
# 44 JMJS    08.11.28 15:42

전자시계 Type A
첨부파일: watch_type_a.zip
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 245
97  test plusargs value plusargs JMJS 24.9.5 293
96  color text JMJS 24.7.13 298
95  draw_hexa.v JMJS 10.6.17 2503
94  jmjsxram3.v JMJS 10.4.9 2267
93  Verilog document JMJS 11.1.24 2876
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2467
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3882
90  gtkwave PC version JMJS 09.3.30 2227
89  ncsim option example JMJS 08.12.1 4610
88  [영상]keywords for web search JMJS 08.12.1 2238
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6489
86  ncverilog option example JMJS 10.6.8 8070
85  [Verilog]Latch example JMJS 08.12.1 2825
84  Pad verilog example JMJS 01.3.16 4733
83  [ModelSim] vector JMJS 01.3.16 2430
82  RTL Code 분석순서 JMJS 09.4.29 2713
81  [temp]PIPE JMJS 08.10.2 2082
80  [temp]always-forever 무한루프 JMJS 08.10.2 2178
79  YCbCr2RGB.v JMJS 10.5.12 2367
78  [VHDL]rom64x8 JMJS 09.3.27 1954
77  [function]vector_compare JMJS 02.6.19 1863
76  [function]vector2integer JMJS 02.6.19 1992
75  [VHDL]ram8x4x8 JMJS 08.12.1 1843
74  [예]shift JMJS 02.6.19 2249
73  test JMJS 09.7.20 2040
72  test JMJS 09.7.20 1754
71  test JMJS 09.7.20 1752
70  test JMJS 09.7.20 1846
69  test JMJS 09.7.20 1891
68  test JMJS 09.7.20 1839
67  test JMJS 09.7.20 1756
66  test JMJS 09.7.20 1735
65  test JMJS 09.7.20 1826
64  test JMJS 09.7.20 2039
63  test JMJS 09.7.20 2052
62  test JMJS 09.7.20 1975
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3780
60  test JMJS 09.7.20 1686
59  test JMJS 09.7.20 1842
58  test JMJS 09.7.20 1817
57  test JMJS 09.7.20 1775
56  test JMJS 09.7.20 1829
55  verilog 학과 샘플강의 JMJS 16.5.30 2374
54  [verilog]create_generated_clock JMJS 15.4.28 2347
53  [Verilog]JDIFF JMJS 14.7.4 1624
52  [verilog]parameter definition JMJS 14.3.5 1928
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4880
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2613
49  Verdi JMJS 10.4.22 3385
48  draw hexa JMJS 10.4.9 1975
47  asfifo - Async FIFO JMJS 10.4.8 1840
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3497
45  synplify batch JMJS 10.3.8 2606
44  전자시계 Type A JMJS 08.11.28 2130
43  I2C Webpage JMJS 08.2.25 1967
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6122
41  [Verilog]vstring JMJS 17.9.27 2196
40  Riviera Simple Case JMJS 09.4.29 3313
39  [VHDL]DES Example JMJS 07.6.15 3108
38  [verilog]RAM example JMJS 09.6.5 2872
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2155
36  Jamie's VHDL Handbook JMJS 08.11.28 2819
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3433
34  RTL Job JMJS 09.4.29 2286
33  [VHDL]type example - package TYPES JMJS 06.2.2 1899
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9485
30  [verilog]array_module JMJS 05.12.8 2409
29  [verilog-2001]generate JMJS 05.12.8 3515
28  protected JMJS 05.11.18 2178
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2976
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1956
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2599
23  Array Of Array JMJS 04.8.16 2115
22  dumpfile, dumpvars JMJS 04.7.19 3746
21  Vending Machine Jamie 02.12.16 10196
20  Mini Vending Machine1 Jamie 02.12.10 7079
19  Mini Vending Machine Jamie 02.12.6 9935
18  Key Jamie 02.11.29 5097
17  Stop Watch Jamie 02.11.25 5741
16  Mealy Machine Jamie 02.8.29 6845
15  Moore Machine Jamie 02.8.29 18152
14  Up Down Counter Jamie 02.8.29 4187
13  Up Counter Jamie 02.8.29 2875
12  Edge Detecter Jamie 02.8.29 3107
11  Concept4 Jamie 02.8.28 2166
10  Concept3 Jamie 02.8.28 2189
9  Concept2_1 Jamie 02.8.28 2078
8  Concept2 Jamie 02.8.28 2168
7  Concept1 Jamie 02.8.26 2322
6  Tri State Buffer Jamie 02.8.26 3675
5  8x3 Encoder Jamie 02.8.28 4293
4  3x8 Decoder Jamie 02.8.28 3951
3  4bit Comparator Jamie 02.8.26 3330
2  가위 바위 보 게임 Jamie 02.8.26 5612
1  Two Input Logic Jamie 02.8.26 2577
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