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전자시계 Type A
# 44 JMJS    08.11.28 15:42

전자시계 Type A
첨부파일: watch_type_a.zip
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 328
97  test plusargs value plusargs JMJS 24.9.5 347
96  color text JMJS 24.7.13 385
95  draw_hexa.v JMJS 10.6.17 2541
94  jmjsxram3.v JMJS 10.4.9 2435
93  Verilog document JMJS 11.1.24 3033
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2621
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4058
90  gtkwave PC version JMJS 09.3.30 2423
89  ncsim option example JMJS 08.12.1 4787
88  [영상]keywords for web search JMJS 08.12.1 2385
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6545
86  ncverilog option example JMJS 10.6.8 8248
85  [Verilog]Latch example JMJS 08.12.1 2988
84  Pad verilog example JMJS 01.3.16 4924
83  [ModelSim] vector JMJS 01.3.16 2616
82  RTL Code 분석순서 JMJS 09.4.29 2863
81  [temp]PIPE JMJS 08.10.2 2258
80  [temp]always-forever 무한루프 JMJS 08.10.2 2336
79  YCbCr2RGB.v JMJS 10.5.12 2533
78  [VHDL]rom64x8 JMJS 09.3.27 2080
77  [function]vector_compare JMJS 02.6.19 1981
76  [function]vector2integer JMJS 02.6.19 2183
75  [VHDL]ram8x4x8 JMJS 08.12.1 1922
74  [예]shift JMJS 02.6.19 2375
73  test JMJS 09.7.20 2219
72  test JMJS 09.7.20 1791
71  test JMJS 09.7.20 1931
70  test JMJS 09.7.20 2026
69  test JMJS 09.7.20 2074
68  test JMJS 09.7.20 2008
67  test JMJS 09.7.20 1944
66  test JMJS 09.7.20 1891
65  test JMJS 09.7.20 2010
64  test JMJS 09.7.20 2205
63  test JMJS 09.7.20 2241
62  test JMJS 09.7.20 2134
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3927
60  test JMJS 09.7.20 1723
59  test JMJS 09.7.20 2062
58  test JMJS 09.7.20 1968
57  test JMJS 09.7.20 1938
56  test JMJS 09.7.20 1977
55  verilog 학과 샘플강의 JMJS 16.5.30 2429
54  [verilog]create_generated_clock JMJS 15.4.28 2410
53  [Verilog]JDIFF JMJS 14.7.4 1800
52  [verilog]parameter definition JMJS 14.3.5 2085
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5023
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2686
49  Verdi JMJS 10.4.22 3568
48  draw hexa JMJS 10.4.9 2074
47  asfifo - Async FIFO JMJS 10.4.8 1935
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3610
45  synplify batch JMJS 10.3.8 2803
44  전자시계 Type A JMJS 08.11.28 2295
43  I2C Webpage JMJS 08.2.25 2131
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6240
41  [Verilog]vstring JMJS 17.9.27 2336
40  Riviera Simple Case JMJS 09.4.29 3431
39  [VHDL]DES Example JMJS 07.6.15 3284
38  [verilog]RAM example JMJS 09.6.5 3063
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2297
36  Jamie's VHDL Handbook JMJS 08.11.28 2990
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3570
34  RTL Job JMJS 09.4.29 2503
33  [VHDL]type example - package TYPES JMJS 06.2.2 1971
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9636
30  [verilog]array_module JMJS 05.12.8 2539
29  [verilog-2001]generate JMJS 05.12.8 3685
28  protected JMJS 05.11.18 2335
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3082
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2073
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2704
23  Array Of Array JMJS 04.8.16 2228
22  dumpfile, dumpvars JMJS 04.7.19 3922
21  Vending Machine Jamie 02.12.16 10359
20  Mini Vending Machine1 Jamie 02.12.10 7230
19  Mini Vending Machine Jamie 02.12.6 10064
18  Key Jamie 02.11.29 5261
17  Stop Watch Jamie 02.11.25 5812
16  Mealy Machine Jamie 02.8.29 6979
15  Moore Machine Jamie 02.8.29 18330
14  Up Down Counter Jamie 02.8.29 4349
13  Up Counter Jamie 02.8.29 3041
12  Edge Detecter Jamie 02.8.29 3256
11  Concept4 Jamie 02.8.28 2231
10  Concept3 Jamie 02.8.28 2321
9  Concept2_1 Jamie 02.8.28 2219
8  Concept2 Jamie 02.8.28 2304
7  Concept1 Jamie 02.8.26 2353
6  Tri State Buffer Jamie 02.8.26 3899
5  8x3 Encoder Jamie 02.8.28 4454
4  3x8 Decoder Jamie 02.8.28 4092
3  4bit Comparator Jamie 02.8.26 3472
2  가위 바위 보 게임 Jamie 02.8.26 5647
1  Two Input Logic Jamie 02.8.26 2723
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