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전자시계 Type A
# 44 JMJS    08.11.28 15:42

전자시계 Type A
첨부파일: watch_type_a.zip
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 363
97  test plusargs value plusargs JMJS 24.9.5 372
96  color text JMJS 24.7.13 421
95  draw_hexa.v JMJS 10.6.17 2570
94  jmjsxram3.v JMJS 10.4.9 2563
93  Verilog document JMJS 11.1.24 3127
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2741
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4161
90  gtkwave PC version JMJS 09.3.30 2544
89  ncsim option example JMJS 08.12.1 4896
88  [영상]keywords for web search JMJS 08.12.1 2501
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6578
86  ncverilog option example JMJS 10.6.8 8372
85  [Verilog]Latch example JMJS 08.12.1 3104
84  Pad verilog example JMJS 01.3.16 5054
83  [ModelSim] vector JMJS 01.3.16 2720
82  RTL Code 분석순서 JMJS 09.4.29 2969
81  [temp]PIPE JMJS 08.10.2 2381
80  [temp]always-forever 무한루프 JMJS 08.10.2 2469
79  YCbCr2RGB.v JMJS 10.5.12 2604
78  [VHDL]rom64x8 JMJS 09.3.27 2181
77  [function]vector_compare JMJS 02.6.19 2023
76  [function]vector2integer JMJS 02.6.19 2311
75  [VHDL]ram8x4x8 JMJS 08.12.1 1991
74  [예]shift JMJS 02.6.19 2460
73  test JMJS 09.7.20 2343
72  test JMJS 09.7.20 1814
71  test JMJS 09.7.20 2074
70  test JMJS 09.7.20 2155
69  test JMJS 09.7.20 2190
68  test JMJS 09.7.20 2135
67  test JMJS 09.7.20 2076
66  test JMJS 09.7.20 2038
65  test JMJS 09.7.20 2149
64  test JMJS 09.7.20 2305
63  test JMJS 09.7.20 2372
62  test JMJS 09.7.20 2268
61  VHDL의 연산자 우선순위 JMJS 09.7.20 4050
60  test JMJS 09.7.20 1747
59  test JMJS 09.7.20 2199
58  test JMJS 09.7.20 2109
57  test JMJS 09.7.20 2053
56  test JMJS 09.7.20 2117
55  verilog 학과 샘플강의 JMJS 16.5.30 2457
54  [verilog]create_generated_clock JMJS 15.4.28 2456
53  [Verilog]JDIFF JMJS 14.7.4 1932
52  [verilog]parameter definition JMJS 14.3.5 2208
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5163
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2722
49  Verdi JMJS 10.4.22 3661
48  draw hexa JMJS 10.4.9 2113
47  asfifo - Async FIFO JMJS 10.4.8 1984
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3692
45  synplify batch JMJS 10.3.8 2896
44  전자시계 Type A JMJS 08.11.28 2434
43  I2C Webpage JMJS 08.2.25 2260
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6268
41  [Verilog]vstring JMJS 17.9.27 2414
40  Riviera Simple Case JMJS 09.4.29 3512
39  [VHDL]DES Example JMJS 07.6.15 3429
38  [verilog]RAM example JMJS 09.6.5 3201
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2433
36  Jamie's VHDL Handbook JMJS 08.11.28 3090
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3698
34  RTL Job JMJS 09.4.29 2625
33  [VHDL]type example - package TYPES JMJS 06.2.2 2009
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9736
30  [verilog]array_module JMJS 05.12.8 2650
29  [verilog-2001]generate JMJS 05.12.8 3798
28  protected JMJS 05.11.18 2492
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3165
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2118
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2798
23  Array Of Array JMJS 04.8.16 2327
22  dumpfile, dumpvars JMJS 04.7.19 4040
21  Vending Machine Jamie 02.12.16 10466
20  Mini Vending Machine1 Jamie 02.12.10 7358
19  Mini Vending Machine Jamie 02.12.6 10140
18  Key Jamie 02.11.29 5374
17  Stop Watch Jamie 02.11.25 5849
16  Mealy Machine Jamie 02.8.29 7083
15  Moore Machine Jamie 02.8.29 18432
14  Up Down Counter Jamie 02.8.29 4496
13  Up Counter Jamie 02.8.29 3177
12  Edge Detecter Jamie 02.8.29 3375
11  Concept4 Jamie 02.8.28 2259
10  Concept3 Jamie 02.8.28 2433
9  Concept2_1 Jamie 02.8.28 2299
8  Concept2 Jamie 02.8.28 2378
7  Concept1 Jamie 02.8.26 2376
6  Tri State Buffer Jamie 02.8.26 4025
5  8x3 Encoder Jamie 02.8.28 4591
4  3x8 Decoder Jamie 02.8.28 4222
3  4bit Comparator Jamie 02.8.26 3596
2  가위 바위 보 게임 Jamie 02.8.26 5672
1  Two Input Logic Jamie 02.8.26 2842
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