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전자시계 Type A
# 44 JMJS    08.11.28 15:42

전자시계 Type A
첨부파일: watch_type_a.zip
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 288
97  test plusargs value plusargs JMJS 24.9.5 330
96  color text JMJS 24.7.13 347
95  draw_hexa.v JMJS 10.6.17 2523
94  jmjsxram3.v JMJS 10.4.9 2348
93  Verilog document JMJS 11.1.24 2963
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2530
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3956
90  gtkwave PC version JMJS 09.3.30 2326
89  ncsim option example JMJS 08.12.1 4701
88  [영상]keywords for web search JMJS 08.12.1 2309
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6523
86  ncverilog option example JMJS 10.6.8 8158
85  [Verilog]Latch example JMJS 08.12.1 2898
84  Pad verilog example JMJS 01.3.16 4831
83  [ModelSim] vector JMJS 01.3.16 2516
82  RTL Code 분석순서 JMJS 09.4.29 2784
81  [temp]PIPE JMJS 08.10.2 2169
80  [temp]always-forever 무한루프 JMJS 08.10.2 2259
79  YCbCr2RGB.v JMJS 10.5.12 2440
78  [VHDL]rom64x8 JMJS 09.3.27 2006
77  [function]vector_compare JMJS 02.6.19 1920
76  [function]vector2integer JMJS 02.6.19 2099
75  [VHDL]ram8x4x8 JMJS 08.12.1 1884
74  [예]shift JMJS 02.6.19 2311
73  test JMJS 09.7.20 2126
72  test JMJS 09.7.20 1775
71  test JMJS 09.7.20 1838
70  test JMJS 09.7.20 1941
69  test JMJS 09.7.20 1980
68  test JMJS 09.7.20 1919
67  test JMJS 09.7.20 1844
66  test JMJS 09.7.20 1810
65  test JMJS 09.7.20 1905
64  test JMJS 09.7.20 2121
63  test JMJS 09.7.20 2140
62  test JMJS 09.7.20 2062
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3852
60  test JMJS 09.7.20 1712
59  test JMJS 09.7.20 1937
58  test JMJS 09.7.20 1889
57  test JMJS 09.7.20 1853
56  test JMJS 09.7.20 1896
55  verilog 학과 샘플강의 JMJS 16.5.30 2407
54  [verilog]create_generated_clock JMJS 15.4.28 2385
53  [Verilog]JDIFF JMJS 14.7.4 1702
52  [verilog]parameter definition JMJS 14.3.5 2005
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4933
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2649
49  Verdi JMJS 10.4.22 3464
48  draw hexa JMJS 10.4.9 2020
47  asfifo - Async FIFO JMJS 10.4.8 1890
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3561
45  synplify batch JMJS 10.3.8 2696
44  전자시계 Type A JMJS 08.11.28 2210
43  I2C Webpage JMJS 08.2.25 2049
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6193
41  [Verilog]vstring JMJS 17.9.27 2266
40  Riviera Simple Case JMJS 09.4.29 3357
39  [VHDL]DES Example JMJS 07.6.15 3194
38  [verilog]RAM example JMJS 09.6.5 2962
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2233
36  Jamie's VHDL Handbook JMJS 08.11.28 2891
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3499
34  RTL Job JMJS 09.4.29 2387
33  [VHDL]type example - package TYPES JMJS 06.2.2 1941
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9564
30  [verilog]array_module JMJS 05.12.8 2462
29  [verilog-2001]generate JMJS 05.12.8 3593
28  protected JMJS 05.11.18 2244
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3019
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2011
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2646
23  Array Of Array JMJS 04.8.16 2163
22  dumpfile, dumpvars JMJS 04.7.19 3824
21  Vending Machine Jamie 02.12.16 10267
20  Mini Vending Machine1 Jamie 02.12.10 7153
19  Mini Vending Machine Jamie 02.12.6 10002
18  Key Jamie 02.11.29 5164
17  Stop Watch Jamie 02.11.25 5780
16  Mealy Machine Jamie 02.8.29 6918
15  Moore Machine Jamie 02.8.29 18246
14  Up Down Counter Jamie 02.8.29 4265
13  Up Counter Jamie 02.8.29 2961
12  Edge Detecter Jamie 02.8.29 3180
11  Concept4 Jamie 02.8.28 2208
10  Concept3 Jamie 02.8.28 2257
9  Concept2_1 Jamie 02.8.28 2144
8  Concept2 Jamie 02.8.28 2236
7  Concept1 Jamie 02.8.26 2341
6  Tri State Buffer Jamie 02.8.26 3785
5  8x3 Encoder Jamie 02.8.28 4389
4  3x8 Decoder Jamie 02.8.28 4021
3  4bit Comparator Jamie 02.8.26 3399
2  가위 바위 보 게임 Jamie 02.8.26 5632
1  Two Input Logic Jamie 02.8.26 2639
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