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test
# 63 JMJS    09.7.20 15:59

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 249
97  test plusargs value plusargs JMJS 24.9.5 296
96  color text JMJS 24.7.13 301
95  draw_hexa.v JMJS 10.6.17 2505
94  jmjsxram3.v JMJS 10.4.9 2269
93  Verilog document JMJS 11.1.24 2883
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2470
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3885
90  gtkwave PC version JMJS 09.3.30 2235
89  ncsim option example JMJS 08.12.1 4613
88  [영상]keywords for web search JMJS 08.12.1 2243
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6491
86  ncverilog option example JMJS 10.6.8 8073
85  [Verilog]Latch example JMJS 08.12.1 2830
84  Pad verilog example JMJS 01.3.16 4738
83  [ModelSim] vector JMJS 01.3.16 2436
82  RTL Code 분석순서 JMJS 09.4.29 2718
81  [temp]PIPE JMJS 08.10.2 2090
80  [temp]always-forever 무한루프 JMJS 08.10.2 2183
79  YCbCr2RGB.v JMJS 10.5.12 2374
78  [VHDL]rom64x8 JMJS 09.3.27 1956
77  [function]vector_compare JMJS 02.6.19 1866
76  [function]vector2integer JMJS 02.6.19 1994
75  [VHDL]ram8x4x8 JMJS 08.12.1 1845
74  [예]shift JMJS 02.6.19 2253
73  test JMJS 09.7.20 2046
72  test JMJS 09.7.20 1756
71  test JMJS 09.7.20 1755
70  test JMJS 09.7.20 1850
69  test JMJS 09.7.20 1896
68  test JMJS 09.7.20 1844
67  test JMJS 09.7.20 1762
66  test JMJS 09.7.20 1742
65  test JMJS 09.7.20 1836
64  test JMJS 09.7.20 2046
63  test JMJS 09.7.20 2057
62  test JMJS 09.7.20 1978
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3789
60  test JMJS 09.7.20 1688
59  test JMJS 09.7.20 1850
58  test JMJS 09.7.20 1824
57  test JMJS 09.7.20 1779
56  test JMJS 09.7.20 1835
55  verilog 학과 샘플강의 JMJS 16.5.30 2376
54  [verilog]create_generated_clock JMJS 15.4.28 2349
53  [Verilog]JDIFF JMJS 14.7.4 1625
52  [verilog]parameter definition JMJS 14.3.5 1935
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4885
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2615
49  Verdi JMJS 10.4.22 3390
48  draw hexa JMJS 10.4.9 1978
47  asfifo - Async FIFO JMJS 10.4.8 1842
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3501
45  synplify batch JMJS 10.3.8 2612
44  전자시계 Type A JMJS 08.11.28 2137
43  I2C Webpage JMJS 08.2.25 1971
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6127
41  [Verilog]vstring JMJS 17.9.27 2200
40  Riviera Simple Case JMJS 09.4.29 3316
39  [VHDL]DES Example JMJS 07.6.15 3118
38  [verilog]RAM example JMJS 09.6.5 2882
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2157
36  Jamie's VHDL Handbook JMJS 08.11.28 2824
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3439
34  RTL Job JMJS 09.4.29 2290
33  [VHDL]type example - package TYPES JMJS 06.2.2 1903
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9490
30  [verilog]array_module JMJS 05.12.8 2414
29  [verilog-2001]generate JMJS 05.12.8 3518
28  protected JMJS 05.11.18 2181
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2980
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1957
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2602
23  Array Of Array JMJS 04.8.16 2119
22  dumpfile, dumpvars JMJS 04.7.19 3747
21  Vending Machine Jamie 02.12.16 10200
20  Mini Vending Machine1 Jamie 02.12.10 7085
19  Mini Vending Machine Jamie 02.12.6 9936
18  Key Jamie 02.11.29 5100
17  Stop Watch Jamie 02.11.25 5744
16  Mealy Machine Jamie 02.8.29 6847
15  Moore Machine Jamie 02.8.29 18155
14  Up Down Counter Jamie 02.8.29 4193
13  Up Counter Jamie 02.8.29 2881
12  Edge Detecter Jamie 02.8.29 3109
11  Concept4 Jamie 02.8.28 2167
10  Concept3 Jamie 02.8.28 2194
9  Concept2_1 Jamie 02.8.28 2081
8  Concept2 Jamie 02.8.28 2172
7  Concept1 Jamie 02.8.26 2325
6  Tri State Buffer Jamie 02.8.26 3681
5  8x3 Encoder Jamie 02.8.28 4297
4  3x8 Decoder Jamie 02.8.28 3953
3  4bit Comparator Jamie 02.8.26 3337
2  가위 바위 보 게임 Jamie 02.8.26 5615
1  Two Input Logic Jamie 02.8.26 2579
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