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test
# 63 JMJS    09.7.20 15:59

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 162
97  test plusargs value plusargs JMJS 24.9.5 226
96  color text JMJS 24.7.13 234
95  draw_hexa.v JMJS 10.6.17 2432
94  jmjsxram3.v JMJS 10.4.9 2160
93  Verilog document JMJS 11.1.24 2755
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2295
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3771
90  gtkwave PC version JMJS 09.3.30 2094
89  ncsim option example JMJS 08.12.1 4489
88  [영상]keywords for web search JMJS 08.12.1 2098
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6428
86  ncverilog option example JMJS 10.6.8 7910
85  [Verilog]Latch example JMJS 08.12.1 2707
84  Pad verilog example JMJS 01.3.16 4630
83  [ModelSim] vector JMJS 01.3.16 2306
82  RTL Code 분석순서 JMJS 09.4.29 2602
81  [temp]PIPE JMJS 08.10.2 1962
80  [temp]always-forever 무한루프 JMJS 08.10.2 2046
79  YCbCr2RGB.v JMJS 10.5.12 2262
78  [VHDL]rom64x8 JMJS 09.3.27 1862
77  [function]vector_compare JMJS 02.6.19 1812
76  [function]vector2integer JMJS 02.6.19 1883
75  [VHDL]ram8x4x8 JMJS 08.12.1 1775
74  [예]shift JMJS 02.6.19 2134
73  test JMJS 09.7.20 1920
72  test JMJS 09.7.20 1707
71  test JMJS 09.7.20 1636
70  test JMJS 09.7.20 1732
69  test JMJS 09.7.20 1780
68  test JMJS 09.7.20 1709
67  test JMJS 09.7.20 1629
66  test JMJS 09.7.20 1586
65  test JMJS 09.7.20 1702
64  test JMJS 09.7.20 1931
63  test JMJS 09.7.20 1936
62  test JMJS 09.7.20 1856
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3660
60  test JMJS 09.7.20 1640
59  test JMJS 09.7.20 1726
58  test JMJS 09.7.20 1702
57  test JMJS 09.7.20 1643
56  test JMJS 09.7.20 1697
55  verilog 학과 샘플강의 JMJS 16.5.30 2312
54  [verilog]create_generated_clock JMJS 15.4.28 2300
53  [Verilog]JDIFF JMJS 14.7.4 1565
52  [verilog]parameter definition JMJS 14.3.5 1829
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4789
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2566
49  Verdi JMJS 10.4.22 3244
48  draw hexa JMJS 10.4.9 1914
47  asfifo - Async FIFO JMJS 10.4.8 1730
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3388
45  synplify batch JMJS 10.3.8 2490
44  전자시계 Type A JMJS 08.11.28 2002
43  I2C Webpage JMJS 08.2.25 1853
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6014
41  [Verilog]vstring JMJS 17.9.27 2095
40  Riviera Simple Case JMJS 09.4.29 3224
39  [VHDL]DES Example JMJS 07.6.15 2982
38  [verilog]RAM example JMJS 09.6.5 2747
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2027
36  Jamie's VHDL Handbook JMJS 08.11.28 2681
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3331
34  RTL Job JMJS 09.4.29 2162
33  [VHDL]type example - package TYPES JMJS 06.2.2 1837
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9367
30  [verilog]array_module JMJS 05.12.8 2306
29  [verilog-2001]generate JMJS 05.12.8 3399
28  protected JMJS 05.11.18 2065
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2876
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1905
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2497
23  Array Of Array JMJS 04.8.16 1999
22  dumpfile, dumpvars JMJS 04.7.19 3619
21  Vending Machine Jamie 02.12.16 10092
20  Mini Vending Machine1 Jamie 02.12.10 6970
19  Mini Vending Machine Jamie 02.12.6 9800
18  Key Jamie 02.11.29 4993
17  Stop Watch Jamie 02.11.25 5691
16  Mealy Machine Jamie 02.8.29 6740
15  Moore Machine Jamie 02.8.29 17972
14  Up Down Counter Jamie 02.8.29 4081
13  Up Counter Jamie 02.8.29 2782
12  Edge Detecter Jamie 02.8.29 2985
11  Concept4 Jamie 02.8.28 2122
10  Concept3 Jamie 02.8.28 2072
9  Concept2_1 Jamie 02.8.28 1960
8  Concept2 Jamie 02.8.28 2030
7  Concept1 Jamie 02.8.26 2250
6  Tri State Buffer Jamie 02.8.26 3552
5  8x3 Encoder Jamie 02.8.28 4167
4  3x8 Decoder Jamie 02.8.28 3845
3  4bit Comparator Jamie 02.8.26 3223
2  가위 바위 보 게임 Jamie 02.8.26 5565
1  Two Input Logic Jamie 02.8.26 2468
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