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[ModelSim] vector
# 83 JMJS    01.3.16 10:10

restart -f
force -repeat 50 clk 1, 0 25
force reset 1 0 ns, 0 310 ns
force addr_in 00000000 0 ns
force csb 1 0 ns
force oeb 1 0 ns
force data 00001011 0 ns
run 230 us
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 336
97  test plusargs value plusargs JMJS 24.9.5 350
96  color text JMJS 24.7.13 390
95  draw_hexa.v JMJS 10.6.17 2544
94  jmjsxram3.v JMJS 10.4.9 2457
93  Verilog document JMJS 11.1.24 3058
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2645
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4081
90  gtkwave PC version JMJS 09.3.30 2454
89  ncsim option example JMJS 08.12.1 4813
88  [영상]keywords for web search JMJS 08.12.1 2416
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6549
86  ncverilog option example JMJS 10.6.8 8276
85  [Verilog]Latch example JMJS 08.12.1 3011
84  Pad verilog example JMJS 01.3.16 4958
83  [ModelSim] vector JMJS 01.3.16 2644
82  RTL Code 분석순서 JMJS 09.4.29 2877
81  [temp]PIPE JMJS 08.10.2 2286
80  [temp]always-forever 무한루프 JMJS 08.10.2 2359
79  YCbCr2RGB.v JMJS 10.5.12 2550
78  [VHDL]rom64x8 JMJS 09.3.27 2105
77  [function]vector_compare JMJS 02.6.19 1993
76  [function]vector2integer JMJS 02.6.19 2210
75  [VHDL]ram8x4x8 JMJS 08.12.1 1930
74  [예]shift JMJS 02.6.19 2393
73  test JMJS 09.7.20 2251
72  test JMJS 09.7.20 1792
71  test JMJS 09.7.20 1962
70  test JMJS 09.7.20 2052
69  test JMJS 09.7.20 2102
68  test JMJS 09.7.20 2042
67  test JMJS 09.7.20 1973
66  test JMJS 09.7.20 1915
65  test JMJS 09.7.20 2045
64  test JMJS 09.7.20 2230
63  test JMJS 09.7.20 2275
62  test JMJS 09.7.20 2160
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3948
60  test JMJS 09.7.20 1725
59  test JMJS 09.7.20 2090
58  test JMJS 09.7.20 1990
57  test JMJS 09.7.20 1963
56  test JMJS 09.7.20 1997
55  verilog 학과 샘플강의 JMJS 16.5.30 2433
54  [verilog]create_generated_clock JMJS 15.4.28 2419
53  [Verilog]JDIFF JMJS 14.7.4 1835
52  [verilog]parameter definition JMJS 14.3.5 2111
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5050
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2694
49  Verdi JMJS 10.4.22 3597
48  draw hexa JMJS 10.4.9 2085
47  asfifo - Async FIFO JMJS 10.4.8 1944
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3625
45  synplify batch JMJS 10.3.8 2830
44  전자시계 Type A JMJS 08.11.28 2322
43  I2C Webpage JMJS 08.2.25 2151
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6245
41  [Verilog]vstring JMJS 17.9.27 2360
40  Riviera Simple Case JMJS 09.4.29 3442
39  [VHDL]DES Example JMJS 07.6.15 3317
38  [verilog]RAM example JMJS 09.6.5 3079
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2326
36  Jamie's VHDL Handbook JMJS 08.11.28 3022
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3599
34  RTL Job JMJS 09.4.29 2534
33  [VHDL]type example - package TYPES JMJS 06.2.2 1976
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9661
30  [verilog]array_module JMJS 05.12.8 2565
29  [verilog-2001]generate JMJS 05.12.8 3708
28  protected JMJS 05.11.18 2373
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3099
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2086
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2717
23  Array Of Array JMJS 04.8.16 2251
22  dumpfile, dumpvars JMJS 04.7.19 3953
21  Vending Machine Jamie 02.12.16 10389
20  Mini Vending Machine1 Jamie 02.12.10 7240
19  Mini Vending Machine Jamie 02.12.6 10079
18  Key Jamie 02.11.29 5292
17  Stop Watch Jamie 02.11.25 5820
16  Mealy Machine Jamie 02.8.29 7009
15  Moore Machine Jamie 02.8.29 18347
14  Up Down Counter Jamie 02.8.29 4371
13  Up Counter Jamie 02.8.29 3066
12  Edge Detecter Jamie 02.8.29 3288
11  Concept4 Jamie 02.8.28 2236
10  Concept3 Jamie 02.8.28 2349
9  Concept2_1 Jamie 02.8.28 2241
8  Concept2 Jamie 02.8.28 2330
7  Concept1 Jamie 02.8.26 2356
6  Tri State Buffer Jamie 02.8.26 3933
5  8x3 Encoder Jamie 02.8.28 4478
4  3x8 Decoder Jamie 02.8.28 4116
3  4bit Comparator Jamie 02.8.26 3488
2  가위 바위 보 게임 Jamie 02.8.26 5649
1  Two Input Logic Jamie 02.8.26 2748
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