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[ModelSim] vector

# 83

JMJS 01.3.16 10:10

restart -f
force -repeat 50 clk 1, 0 25
force reset 1 0 ns, 0 310 ns
force addr_in 00000000 0 ns
force csb 1 0 ns
force oeb 1 0 ns
force data 00001011 0 ns
run 230 us

게시물: 96 건, 현재: 1 / 1 쪽
번호	제 목	작성자	등록일	방문
98	interface	JMJS	25.1.20	179
97	test plusargs value plusargs	JMJS	24.9.5	246
96	color text	JMJS	24.7.13	251
95	draw_hexa.v	JMJS	10.6.17	2454
94	jmjsxram3.v	JMJS	10.4.9	2185
93	Verilog document	JMJS	11.1.24	2795
92	[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;	JMJS	09.3.31	2380
91	[verilog]forever, repeat, strobe, realtime, ...	JMJS	09.7.6	3797
90	gtkwave PC version	JMJS	09.3.30	2131
89	ncsim option example	JMJS	08.12.1	4518
88	[영상]keywords for web search	JMJS	08.12.1	2149
87	[Verilog]fdisplay fopen fscanf	JMJS	11.1.24	6456
86	ncverilog option example	JMJS	10.6.8	7975
85	[Verilog]Latch example	JMJS	08.12.1	2732
84	Pad verilog example	JMJS	01.3.16	4661
83	[ModelSim] vector	JMJS	01.3.16	2350
82	RTL Code 분석순서	JMJS	09.4.29	2628
81	[temp]PIPE	JMJS	08.10.2	1998
80	[temp]always-forever 무한루프	JMJS	08.10.2	2072
79	YCbCr2RGB.v	JMJS	10.5.12	2300
78	[VHDL]rom64x8	JMJS	09.3.27	1884
77	[function]vector_compare	JMJS	02.6.19	1830
76	[function]vector2integer	JMJS	02.6.19	1923
75	[VHDL]ram8x4x8	JMJS	08.12.1	1797
74	[예]shift	JMJS	02.6.19	2160
73	test	JMJS	09.7.20	1949
72	test	JMJS	09.7.20	1722
71	test	JMJS	09.7.20	1668
70	test	JMJS	09.7.20	1760
69	test	JMJS	09.7.20	1805
68	test	JMJS	09.7.20	1748
67	test	JMJS	09.7.20	1661
66	test	JMJS	09.7.20	1639
65	test	JMJS	09.7.20	1739
64	test	JMJS	09.7.20	1958
63	test	JMJS	09.7.20	1975
62	test	JMJS	09.7.20	1884
61	VHDL의 연산자 우선순위	JMJS	09.7.20	3689
60	test	JMJS	09.7.20	1656
59	test	JMJS	09.7.20	1764
58	test	JMJS	09.7.20	1730
57	test	JMJS	09.7.20	1693
56	test	JMJS	09.7.20	1731
55	verilog 학과 샘플강의	JMJS	16.5.30	2326
54	[verilog]create_generated_clock	JMJS	15.4.28	2317
53	[Verilog]JDIFF	JMJS	14.7.4	1582
52	[verilog]parameter definition	JMJS	14.3.5	1856
51	[verilog]sformat fopen fscanf fwrite fclose	JMJS	12.1.31	4808
50	Verilog File I/0,Verilog file handling	JMJS	12.1.30	2580
49	Verdi	JMJS	10.4.22	3301
48	draw hexa	JMJS	10.4.9	1935
47	asfifo - Async FIFO	JMJS	10.4.8	1782
46	VHDL을 이용한 회로설계의 장점	JMJS	02.3.14	3412
45	synplify batch	JMJS	10.3.8	2522
44	전자시계 Type A	JMJS	08.11.28	2041
43	I2C Webpage	JMJS	08.2.25	1882
42	PC에서 간단히 Verilog 실행해보기 (Icarus Verilog)	JMJS	13.1.14	6040
41	[Verilog]vstring	JMJS	17.9.27	2126
40	Riviera Simple Case	JMJS	09.4.29	3255
39	[VHDL]DES Example	JMJS	07.6.15	3013
38	[verilog]RAM example	JMJS	09.6.5	2776
37	ROM example [VerilogHDL, RTL]	JMJS	04.5.27	2058
36	Jamie's VHDL Handbook	JMJS	08.11.28	2732
35	Dualport RAM example [VerilogHDL, RTL]	JMJS	04.5.27	3359
34	RTL Job	JMJS	09.4.29	2198
33	[VHDL]type example - package TYPES	JMJS	06.2.2	1862
32	[verilog]`define `ifdef `elsif `else `endif ...	JMJS	10.5.11	9404
30	[verilog]array_module	JMJS	05.12.8	2339
29	[verilog-2001]generate	JMJS	05.12.8	3417
28	protected	JMJS	05.11.18	2095
27	design에 latch가 있으면 안되나요?	JMJS	09.7.20	2912
26	bus의 데이타를 각 bit별로 출력하는 방법은?	JMJS	04.11.9	1924
25	component를 생성해서 다른 곳에서 호출하는 방법	JMJS	04.11.4	2531
23	Array Of Array	JMJS	04.8.16	2042
22	dumpfile, dumpvars	JMJS	04.7.19	3651
21	Vending Machine	Jamie	02.12.16	10121
20	Mini Vending Machine1	Jamie	02.12.10	7003
19	Mini Vending Machine	Jamie	02.12.6	9853
18	Key	Jamie	02.11.29	5019
17	Stop Watch	Jamie	02.11.25	5705
16	Mealy Machine	Jamie	02.8.29	6774
15	Moore Machine	Jamie	02.8.29	18006
14	Up Down Counter	Jamie	02.8.29	4112
13	Up Counter	Jamie	02.8.29	2812
12	Edge Detecter	Jamie	02.8.29	3026
11	Concept4	Jamie	02.8.28	2136
10	Concept3	Jamie	02.8.28	2112
9	Concept2_1	Jamie	02.8.28	1993
8	Concept2	Jamie	02.8.28	2085
7	Concept1	Jamie	02.8.26	2289
6	Tri State Buffer	Jamie	02.8.26	3587
5	8x3 Encoder	Jamie	02.8.28	4209
4	3x8 Decoder	Jamie	02.8.28	3872
3	4bit Comparator	Jamie	02.8.26	3248
2	가위 바위 보 게임	Jamie	02.8.26	5580
1	Two Input Logic	Jamie	02.8.26	2492

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