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[ModelSim] vector

# 83

JMJS 01.3.16 10:10

restart -f
force -repeat 50 clk 1, 0 25
force reset 1 0 ns, 0 310 ns
force addr_in 00000000 0 ns
force csb 1 0 ns
force oeb 1 0 ns
force data 00001011 0 ns
run 230 us

게시물: 96 건, 현재: 1 / 1 쪽
번호	제 목	작성자	등록일	방문
98	interface	JMJS	25.1.20	357
97	test plusargs value plusargs	JMJS	24.9.5	365
96	color text	JMJS	24.7.13	418
95	draw_hexa.v	JMJS	10.6.17	2567
94	jmjsxram3.v	JMJS	10.4.9	2557
93	Verilog document	JMJS	11.1.24	3122
92	[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;	JMJS	09.3.31	2730
91	[verilog]forever, repeat, strobe, realtime, ...	JMJS	09.7.6	4156
90	gtkwave PC version	JMJS	09.3.30	2539
89	ncsim option example	JMJS	08.12.1	4890
88	[영상]keywords for web search	JMJS	08.12.1	2491
87	[Verilog]fdisplay fopen fscanf	JMJS	11.1.24	6577
86	ncverilog option example	JMJS	10.6.8	8364
85	[Verilog]Latch example	JMJS	08.12.1	3093
84	Pad verilog example	JMJS	01.3.16	5043
83	[ModelSim] vector	JMJS	01.3.16	2713
82	RTL Code 분석순서	JMJS	09.4.29	2962
81	[temp]PIPE	JMJS	08.10.2	2374
80	[temp]always-forever 무한루프	JMJS	08.10.2	2462
79	YCbCr2RGB.v	JMJS	10.5.12	2600
78	[VHDL]rom64x8	JMJS	09.3.27	2174
77	[function]vector_compare	JMJS	02.6.19	2021
76	[function]vector2integer	JMJS	02.6.19	2300
75	[VHDL]ram8x4x8	JMJS	08.12.1	1985
74	[예]shift	JMJS	02.6.19	2456
73	test	JMJS	09.7.20	2334
72	test	JMJS	09.7.20	1811
71	test	JMJS	09.7.20	2064
70	test	JMJS	09.7.20	2147
69	test	JMJS	09.7.20	2183
68	test	JMJS	09.7.20	2127
67	test	JMJS	09.7.20	2068
66	test	JMJS	09.7.20	2032
65	test	JMJS	09.7.20	2143
64	test	JMJS	09.7.20	2300
63	test	JMJS	09.7.20	2361
62	test	JMJS	09.7.20	2256
61	VHDL의 연산자 우선순위	JMJS	09.7.20	4045
60	test	JMJS	09.7.20	1743
59	test	JMJS	09.7.20	2189
58	test	JMJS	09.7.20	2103
57	test	JMJS	09.7.20	2046
56	test	JMJS	09.7.20	2109
55	verilog 학과 샘플강의	JMJS	16.5.30	2456
54	[verilog]create_generated_clock	JMJS	15.4.28	2448
53	[Verilog]JDIFF	JMJS	14.7.4	1924
52	[verilog]parameter definition	JMJS	14.3.5	2200
51	[verilog]sformat fopen fscanf fwrite fclose	JMJS	12.1.31	5155
50	Verilog File I/0,Verilog file handling	JMJS	12.1.30	2720
49	Verdi	JMJS	10.4.22	3657
48	draw hexa	JMJS	10.4.9	2108
47	asfifo - Async FIFO	JMJS	10.4.8	1979
46	VHDL을 이용한 회로설계의 장점	JMJS	02.3.14	3683
45	synplify batch	JMJS	10.3.8	2889
44	전자시계 Type A	JMJS	08.11.28	2426
43	I2C Webpage	JMJS	08.2.25	2251
42	PC에서 간단히 Verilog 실행해보기 (Icarus Verilog)	JMJS	13.1.14	6266
41	[Verilog]vstring	JMJS	17.9.27	2406
40	Riviera Simple Case	JMJS	09.4.29	3507
39	[VHDL]DES Example	JMJS	07.6.15	3418
38	[verilog]RAM example	JMJS	09.6.5	3194
37	ROM example [VerilogHDL, RTL]	JMJS	04.5.27	2426
36	Jamie's VHDL Handbook	JMJS	08.11.28	3083
35	Dualport RAM example [VerilogHDL, RTL]	JMJS	04.5.27	3691
34	RTL Job	JMJS	09.4.29	2617
33	[VHDL]type example - package TYPES	JMJS	06.2.2	2008
32	[verilog]`define `ifdef `elsif `else `endif ...	JMJS	10.5.11	9727
30	[verilog]array_module	JMJS	05.12.8	2641
29	[verilog-2001]generate	JMJS	05.12.8	3788
28	protected	JMJS	05.11.18	2483
27	design에 latch가 있으면 안되나요?	JMJS	09.7.20	3159
26	bus의 데이타를 각 bit별로 출력하는 방법은?	JMJS	04.11.9	2113
25	component를 생성해서 다른 곳에서 호출하는 방법	JMJS	04.11.4	2784
23	Array Of Array	JMJS	04.8.16	2321
22	dumpfile, dumpvars	JMJS	04.7.19	4031
21	Vending Machine	Jamie	02.12.16	10460
20	Mini Vending Machine1	Jamie	02.12.10	7349
19	Mini Vending Machine	Jamie	02.12.6	10133
18	Key	Jamie	02.11.29	5364
17	Stop Watch	Jamie	02.11.25	5847
16	Mealy Machine	Jamie	02.8.29	7075
15	Moore Machine	Jamie	02.8.29	18423
14	Up Down Counter	Jamie	02.8.29	4488
13	Up Counter	Jamie	02.8.29	3170
12	Edge Detecter	Jamie	02.8.29	3365
11	Concept4	Jamie	02.8.28	2257
10	Concept3	Jamie	02.8.28	2425
9	Concept2_1	Jamie	02.8.28	2296
8	Concept2	Jamie	02.8.28	2373
7	Concept1	Jamie	02.8.26	2373
6	Tri State Buffer	Jamie	02.8.26	4016
5	8x3 Encoder	Jamie	02.8.28	4583
4	3x8 Decoder	Jamie	02.8.28	4212
3	4bit Comparator	Jamie	02.8.26	3587
2	가위 바위 보 게임	Jamie	02.8.26	5670
1	Two Input Logic	Jamie	02.8.26	2834

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