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[ModelSim] vector
# 83 JMJS    01.3.16 10:10

restart -f
force -repeat 50 clk 1, 0 25
force reset 1 0 ns, 0 310 ns
force addr_in 00000000 0 ns
force csb 1 0 ns
force oeb 1 0 ns
force data 00001011 0 ns
run 230 us

게시물: 93 건, 현재: 1 / 1 쪽
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번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2054
94  jmjsxram3.v JMJS 10.4.9 1795
93  Verilog document JMJS 11.1.24 2388
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1946
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3441
90  gtkwave PC version JMJS 09.3.30 1738
89  ncsim option example JMJS 08.12.1 4133
88  [영상]keywords for web search JMJS 08.12.1 1769
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6120
86  ncverilog option example JMJS 10.6.8 7499
85  [Verilog]Latch example JMJS 08.12.1 2353
84  Pad verilog example JMJS 01.3.16 4292
83  [ModelSim] vector JMJS 01.3.16 1967
82  RTL Code 분석순서 JMJS 09.4.29 2255
81  [temp]PIPE JMJS 08.10.2 1633
80  [temp]always-forever 무한루프 JMJS 08.10.2 1699
79  YCbCr2RGB.v JMJS 10.5.12 1914
78  [VHDL]rom64x8 JMJS 09.3.27 1525
77  [function]vector_compare JMJS 02.6.19 1492
76  [function]vector2integer JMJS 02.6.19 1563
75  [VHDL]ram8x4x8 JMJS 08.12.1 1429
74  [예]shift JMJS 02.6.19 1797
73  test JMJS 09.7.20 1557
72  test JMJS 09.7.20 1373
71  test JMJS 09.7.20 1321
70  test JMJS 09.7.20 1409
69  test JMJS 09.7.20 1446
68  test JMJS 09.7.20 1372
67  test JMJS 09.7.20 1288
66  test JMJS 09.7.20 1265
65  test JMJS 09.7.20 1356
64  test JMJS 09.7.20 1627
63  test JMJS 09.7.20 1622
62  test JMJS 09.7.20 1546
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3409
60  test JMJS 09.7.20 1279
59  test JMJS 09.7.20 1372
58  test JMJS 09.7.20 1403
57  test JMJS 09.7.20 1319
56  test JMJS 09.7.20 1372
55  verilog 학과 샘플강의 JMJS 16.5.30 2038
54  [verilog]create_generated_clock JMJS 15.4.28 1972
53  [Verilog]JDIFF JMJS 14.7.4 1241
52  [verilog]parameter definition JMJS 14.3.5 1502
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4459
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2230
49  Verdi JMJS 10.4.22 2869
48  draw hexa JMJS 10.4.9 1589
47  asfifo - Async FIFO JMJS 10.4.8 1417
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3088
45  synplify batch JMJS 10.3.8 2178
44  전자시계 Type A JMJS 08.11.28 1674
43  I2C Webpage JMJS 08.2.25 1543
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5887
41  [Verilog]vstring JMJS 17.9.27 1780
40  Riviera Simple Case JMJS 09.4.29 2954
39  [VHDL]DES Example JMJS 07.6.15 2658
38  [verilog]RAM example JMJS 09.6.5 2457
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1685
36  Jamie's VHDL Handbook JMJS 08.11.28 2336
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2965
34  RTL Job JMJS 09.4.29 1821
33  [VHDL]type example - package TYPES JMJS 06.2.2 1516
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9375
30  [verilog]array_module JMJS 05.12.8 1896
29  [verilog-2001]generate JMJS 05.12.8 3111
28  protected JMJS 05.11.18 1716
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2556
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1597
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2150
23  Array Of Array JMJS 04.8.16 1717
22  dumpfile, dumpvars JMJS 04.7.19 3347
21  Vending Machine Jamie 02.12.16 9875
20  Mini Vending Machine1 Jamie 02.12.10 6651
19  Mini Vending Machine Jamie 02.12.6 9553
18  Key Jamie 02.11.29 4713
17  Stop Watch Jamie 02.11.25 5428
16  Mealy Machine Jamie 02.8.29 6452
15  Moore Machine Jamie 02.8.29 17094
14  Up Down Counter Jamie 02.8.29 3715
13  Up Counter Jamie 02.8.29 2455
12  Edge Detecter Jamie 02.8.29 2699
11  Concept4 Jamie 02.8.28 1805
10  Concept3 Jamie 02.8.28 1762
9  Concept2_1 Jamie 02.8.28 1650
8  Concept2 Jamie 02.8.28 1723
7  Concept1 Jamie 02.8.26 1949
6  Tri State Buffer Jamie 02.8.26 3247
5  8x3 Encoder Jamie 02.8.28 3882
4  3x8 Decoder Jamie 02.8.28 3567
3  4bit Comparator Jamie 02.8.26 2914
2  가위 바위 보 게임 Jamie 02.8.26 5317
1  Two Input Logic Jamie 02.8.26 2174
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