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[ModelSim] vector

# 83

JMJS 01.3.16 10:10

restart -f
force -repeat 50 clk 1, 0 25
force reset 1 0 ns, 0 310 ns
force addr_in 00000000 0 ns
force csb 1 0 ns
force oeb 1 0 ns
force data 00001011 0 ns
run 230 us

게시물: 96 건, 현재: 1 / 1 쪽
번호	제 목	작성자	등록일	방문
98	interface	JMJS	25.1.20	355
97	test plusargs value plusargs	JMJS	24.9.5	362
96	color text	JMJS	24.7.13	415
95	draw_hexa.v	JMJS	10.6.17	2565
94	jmjsxram3.v	JMJS	10.4.9	2544
93	Verilog document	JMJS	11.1.24	3112
92	[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;	JMJS	09.3.31	2722
91	[verilog]forever, repeat, strobe, realtime, ...	JMJS	09.7.6	4150
90	gtkwave PC version	JMJS	09.3.30	2534
89	ncsim option example	JMJS	08.12.1	4886
88	[영상]keywords for web search	JMJS	08.12.1	2486
87	[Verilog]fdisplay fopen fscanf	JMJS	11.1.24	6574
86	ncverilog option example	JMJS	10.6.8	8358
85	[Verilog]Latch example	JMJS	08.12.1	3082
84	Pad verilog example	JMJS	01.3.16	5033
83	[ModelSim] vector	JMJS	01.3.16	2708
82	RTL Code 분석순서	JMJS	09.4.29	2957
81	[temp]PIPE	JMJS	08.10.2	2367
80	[temp]always-forever 무한루프	JMJS	08.10.2	2455
79	YCbCr2RGB.v	JMJS	10.5.12	2597
78	[VHDL]rom64x8	JMJS	09.3.27	2164
77	[function]vector_compare	JMJS	02.6.19	2019
76	[function]vector2integer	JMJS	02.6.19	2289
75	[VHDL]ram8x4x8	JMJS	08.12.1	1979
74	[예]shift	JMJS	02.6.19	2452
73	test	JMJS	09.7.20	2325
72	test	JMJS	09.7.20	1810
71	test	JMJS	09.7.20	2058
70	test	JMJS	09.7.20	2133
69	test	JMJS	09.7.20	2176
68	test	JMJS	09.7.20	2120
67	test	JMJS	09.7.20	2059
66	test	JMJS	09.7.20	2019
65	test	JMJS	09.7.20	2133
64	test	JMJS	09.7.20	2296
63	test	JMJS	09.7.20	2353
62	test	JMJS	09.7.20	2244
61	VHDL의 연산자 우선순위	JMJS	09.7.20	4033
60	test	JMJS	09.7.20	1742
59	test	JMJS	09.7.20	2176
58	test	JMJS	09.7.20	2091
57	test	JMJS	09.7.20	2036
56	test	JMJS	09.7.20	2097
55	verilog 학과 샘플강의	JMJS	16.5.30	2451
54	[verilog]create_generated_clock	JMJS	15.4.28	2446
53	[Verilog]JDIFF	JMJS	14.7.4	1916
52	[verilog]parameter definition	JMJS	14.3.5	2193
51	[verilog]sformat fopen fscanf fwrite fclose	JMJS	12.1.31	5146
50	Verilog File I/0,Verilog file handling	JMJS	12.1.30	2716
49	Verdi	JMJS	10.4.22	3655
48	draw hexa	JMJS	10.4.9	2107
47	asfifo - Async FIFO	JMJS	10.4.8	1977
46	VHDL을 이용한 회로설계의 장점	JMJS	02.3.14	3679
45	synplify batch	JMJS	10.3.8	2882
44	전자시계 Type A	JMJS	08.11.28	2414
43	I2C Webpage	JMJS	08.2.25	2238
42	PC에서 간단히 Verilog 실행해보기 (Icarus Verilog)	JMJS	13.1.14	6265
41	[Verilog]vstring	JMJS	17.9.27	2399
40	Riviera Simple Case	JMJS	09.4.29	3499
39	[VHDL]DES Example	JMJS	07.6.15	3404
38	[verilog]RAM example	JMJS	09.6.5	3182
37	ROM example [VerilogHDL, RTL]	JMJS	04.5.27	2412
36	Jamie's VHDL Handbook	JMJS	08.11.28	3076
35	Dualport RAM example [VerilogHDL, RTL]	JMJS	04.5.27	3684
34	RTL Job	JMJS	09.4.29	2609
33	[VHDL]type example - package TYPES	JMJS	06.2.2	2005
32	[verilog]`define `ifdef `elsif `else `endif ...	JMJS	10.5.11	9720
30	[verilog]array_module	JMJS	05.12.8	2628
29	[verilog-2001]generate	JMJS	05.12.8	3780
28	protected	JMJS	05.11.18	2472
27	design에 latch가 있으면 안되나요?	JMJS	09.7.20	3153
26	bus의 데이타를 각 bit별로 출력하는 방법은?	JMJS	04.11.9	2111
25	component를 생성해서 다른 곳에서 호출하는 방법	JMJS	04.11.4	2773
23	Array Of Array	JMJS	04.8.16	2313
22	dumpfile, dumpvars	JMJS	04.7.19	4024
21	Vending Machine	Jamie	02.12.16	10454
20	Mini Vending Machine1	Jamie	02.12.10	7334
19	Mini Vending Machine	Jamie	02.12.6	10128
18	Key	Jamie	02.11.29	5355
17	Stop Watch	Jamie	02.11.25	5846
16	Mealy Machine	Jamie	02.8.29	7070
15	Moore Machine	Jamie	02.8.29	18416
14	Up Down Counter	Jamie	02.8.29	4477
13	Up Counter	Jamie	02.8.29	3160
12	Edge Detecter	Jamie	02.8.29	3357
11	Concept4	Jamie	02.8.28	2254
10	Concept3	Jamie	02.8.28	2418
9	Concept2_1	Jamie	02.8.28	2291
8	Concept2	Jamie	02.8.28	2371
7	Concept1	Jamie	02.8.26	2372
6	Tri State Buffer	Jamie	02.8.26	4008
5	8x3 Encoder	Jamie	02.8.28	4571
4	3x8 Decoder	Jamie	02.8.28	4198
3	4bit Comparator	Jamie	02.8.26	3573
2	가위 바위 보 게임	Jamie	02.8.26	5666
1	Two Input Logic	Jamie	02.8.26	2826

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