module adder_generate1 (co, sum, a, b, ci);
  parameter SIZE = 4;
  output [SIZE-1:0] sum;
  output            co;
  input  [SIZE-1:0] a, b;
  input             ci;
  wire   [SIZE  :0] c;
  wire   [SIZE-1:0] t [1:3];
  genvar            i;

  assign c[0] = ci;

  generate
    for (i=0; i<SIZE; i=i+1) begin:bit
      xor g1 (t[1][i],    a[i],    b[i]);
      xor g2 ( sum[i], t[1][i],    c[i]);
      and g3 (t[2][i],    a[i],    b[i]);
      and g4 (t[3][i], t[1][i],    c[i]);
      or  g5 ( c[i+1], t[2][i], t[3][i]);
    end
  endgenerate

  assign co = c[SIZE];
endmodule

module signal_generate2 (in1, in2, out1, out2);
  parameter SIZE = 4;
  input  [SIZE-1:0] in1;
  input  [SIZE-1:0] in2;
  output [SIZE-1:0] out1;
  output [SIZE-1:0] out2;
  genvar            i;

  generate
    for (i=0; i<SIZE; i=i+1) begin:test
      invert invert1 (in1[i], out1[i]);
      buffer buffer1 (in2[i], out2[i]);
    end
  endgenerate

endmodule

module invert(in, out);
  input  in;
  output out;

  assign out = ~in;

endmodule