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test
# 68 JMJS    09.7.20 15:58

test
게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1890
94  jmjsxram3.v JMJS 10.4.9 1676
93  Verilog document JMJS 11.1.24 2239
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1810
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3252
90  gtkwave PC version JMJS 09.3.30 1636
89  ncsim option example JMJS 08.12.1 3948
88  [영상]keywords for web search JMJS 08.12.1 1623
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5893
86  ncverilog option example JMJS 10.6.8 7227
85  [Verilog]Latch example JMJS 08.12.1 2251
84  Pad verilog example JMJS 01.3.16 4132
83  [ModelSim] vector JMJS 01.3.16 1830
82  RTL Code 분석순서 JMJS 09.4.29 2116
81  [temp]PIPE JMJS 08.10.2 1524
80  [temp]always-forever 무한루프 JMJS 08.10.2 1576
79  YCbCr2RGB.v JMJS 10.5.12 1775
78  [VHDL]rom64x8 JMJS 09.3.27 1394
77  [function]vector_compare JMJS 02.6.19 1342
76  [function]vector2integer JMJS 02.6.19 1446
75  [VHDL]ram8x4x8 JMJS 08.12.1 1326
74  [예]shift JMJS 02.6.19 1644
73  test JMJS 09.7.20 1432
72  test JMJS 09.7.20 1266
71  test JMJS 09.7.20 1189
70  test JMJS 09.7.20 1319
69  test JMJS 09.7.20 1339
68  test JMJS 09.7.20 1252
67  test JMJS 09.7.20 1166
66  test JMJS 09.7.20 1145
65  test JMJS 09.7.20 1251
64  test JMJS 09.7.20 1481
63  test JMJS 09.7.20 1470
62  test JMJS 09.7.20 1396
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3142
60  test JMJS 09.7.20 1173
59  test JMJS 09.7.20 1256
58  test JMJS 09.7.20 1274
57  test JMJS 09.7.20 1204
56  test JMJS 09.7.20 1275
55  verilog 학과 샘플강의 JMJS 16.5.30 1818
54  [verilog]create_generated_clock JMJS 15.4.28 1808
53  [Verilog]JDIFF JMJS 14.7.4 1140
52  [verilog]parameter definition JMJS 14.3.5 1400
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4233
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2086
49  Verdi JMJS 10.4.22 2643
48  draw hexa JMJS 10.4.9 1471
47  asfifo - Async FIFO JMJS 10.4.8 1299
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2909
45  synplify batch JMJS 10.3.8 2039
44  전자시계 Type A JMJS 08.11.28 1556
43  I2C Webpage JMJS 08.2.25 1414
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5365
41  [Verilog]vstring JMJS 17.9.27 1670
40  Riviera Simple Case JMJS 09.4.29 2766
39  [VHDL]DES Example JMJS 07.6.15 2534
38  [verilog]RAM example JMJS 09.6.5 2312
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1593
36  Jamie's VHDL Handbook JMJS 08.11.28 2218
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2841
34  RTL Job JMJS 09.4.29 1692
33  [VHDL]type example - package TYPES JMJS 06.2.2 1382
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8772
30  [verilog]array_module JMJS 05.12.8 1743
29  [verilog-2001]generate JMJS 05.12.8 2948
28  protected JMJS 05.11.18 1582
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2416
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1510
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2015
23  Array Of Array JMJS 04.8.16 1592
22  dumpfile, dumpvars JMJS 04.7.19 3183
21  Vending Machine Jamie 02.12.16 9574
20  Mini Vending Machine1 Jamie 02.12.10 6408
19  Mini Vending Machine Jamie 02.12.6 9227
18  Key Jamie 02.11.29 4525
17  Stop Watch Jamie 02.11.25 5269
16  Mealy Machine Jamie 02.8.29 6104
15  Moore Machine Jamie 02.8.29 16430
14  Up Down Counter Jamie 02.8.29 3543
13  Up Counter Jamie 02.8.29 2333
12  Edge Detecter Jamie 02.8.29 2500
11  Concept4 Jamie 02.8.28 1658
10  Concept3 Jamie 02.8.28 1654
9  Concept2_1 Jamie 02.8.28 1518
8  Concept2 Jamie 02.8.28 1611
7  Concept1 Jamie 02.8.26 1803
6  Tri State Buffer Jamie 02.8.26 3081
5  8x3 Encoder Jamie 02.8.28 3669
4  3x8 Decoder Jamie 02.8.28 3350
3  4bit Comparator Jamie 02.8.26 2774
2  가위 바위 보 게임 Jamie 02.8.26 5080
1  Two Input Logic Jamie 02.8.26 2054
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