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test
# 68 JMJS    09.7.20 15:58

test
게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1988
94  jmjsxram3.v JMJS 10.4.9 1727
93  Verilog document JMJS 11.1.24 2309
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1888
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3364
90  gtkwave PC version JMJS 09.3.30 1688
89  ncsim option example JMJS 08.12.1 4069
88  [영상]keywords for web search JMJS 08.12.1 1708
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6018
86  ncverilog option example JMJS 10.6.8 7376
85  [Verilog]Latch example JMJS 08.12.1 2309
84  Pad verilog example JMJS 01.3.16 4222
83  [ModelSim] vector JMJS 01.3.16 1912
82  RTL Code 분석순서 JMJS 09.4.29 2201
81  [temp]PIPE JMJS 08.10.2 1577
80  [temp]always-forever 무한루프 JMJS 08.10.2 1643
79  YCbCr2RGB.v JMJS 10.5.12 1859
78  [VHDL]rom64x8 JMJS 09.3.27 1475
77  [function]vector_compare JMJS 02.6.19 1436
76  [function]vector2integer JMJS 02.6.19 1504
75  [VHDL]ram8x4x8 JMJS 08.12.1 1383
74  [예]shift JMJS 02.6.19 1736
73  test JMJS 09.7.20 1507
72  test JMJS 09.7.20 1324
71  test JMJS 09.7.20 1258
70  test JMJS 09.7.20 1365
69  test JMJS 09.7.20 1396
68  test JMJS 09.7.20 1320
67  test JMJS 09.7.20 1236
66  test JMJS 09.7.20 1199
65  test JMJS 09.7.20 1308
64  test JMJS 09.7.20 1568
63  test JMJS 09.7.20 1554
62  test JMJS 09.7.20 1482
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3289
60  test JMJS 09.7.20 1229
59  test JMJS 09.7.20 1318
58  test JMJS 09.7.20 1348
57  test JMJS 09.7.20 1282
56  test JMJS 09.7.20 1328
55  verilog 학과 샘플강의 JMJS 16.5.30 1942
54  [verilog]create_generated_clock JMJS 15.4.28 1911
53  [Verilog]JDIFF JMJS 14.7.4 1198
52  [verilog]parameter definition JMJS 14.3.5 1455
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4361
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2177
49  Verdi JMJS 10.4.22 2751
48  draw hexa JMJS 10.4.9 1541
47  asfifo - Async FIFO JMJS 10.4.8 1375
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3002
45  synplify batch JMJS 10.3.8 2122
44  전자시계 Type A JMJS 08.11.28 1612
43  I2C Webpage JMJS 08.2.25 1493
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5673
41  [Verilog]vstring JMJS 17.9.27 1727
40  Riviera Simple Case JMJS 09.4.29 2862
39  [VHDL]DES Example JMJS 07.6.15 2608
38  [verilog]RAM example JMJS 09.6.5 2391
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1644
36  Jamie's VHDL Handbook JMJS 08.11.28 2297
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2917
34  RTL Job JMJS 09.4.29 1763
33  [VHDL]type example - package TYPES JMJS 06.2.2 1455
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8994
30  [verilog]array_module JMJS 05.12.8 1840
29  [verilog-2001]generate JMJS 05.12.8 3030
28  protected JMJS 05.11.18 1657
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2491
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1563
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2103
23  Array Of Array JMJS 04.8.16 1648
22  dumpfile, dumpvars JMJS 04.7.19 3278
21  Vending Machine Jamie 02.12.16 9747
20  Mini Vending Machine1 Jamie 02.12.10 6543
19  Mini Vending Machine Jamie 02.12.6 9394
18  Key Jamie 02.11.29 4630
17  Stop Watch Jamie 02.11.25 5337
16  Mealy Machine Jamie 02.8.29 6271
15  Moore Machine Jamie 02.8.29 16707
14  Up Down Counter Jamie 02.8.29 3628
13  Up Counter Jamie 02.8.29 2417
12  Edge Detecter Jamie 02.8.29 2610
11  Concept4 Jamie 02.8.28 1756
10  Concept3 Jamie 02.8.28 1714
9  Concept2_1 Jamie 02.8.28 1600
8  Concept2 Jamie 02.8.28 1676
7  Concept1 Jamie 02.8.26 1877
6  Tri State Buffer Jamie 02.8.26 3180
5  8x3 Encoder Jamie 02.8.28 3772
4  3x8 Decoder Jamie 02.8.28 3455
3  4bit Comparator Jamie 02.8.26 2843
2  가위 바위 보 게임 Jamie 02.8.26 5204
1  Two Input Logic Jamie 02.8.26 2113
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