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test
# 68 JMJS    09.7.20 15:58

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 300
97  test plusargs value plusargs JMJS 24.9.5 336
96  color text JMJS 24.7.13 364
95  draw_hexa.v JMJS 10.6.17 2531
94  jmjsxram3.v JMJS 10.4.9 2387
93  Verilog document JMJS 11.1.24 2988
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2569
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3994
90  gtkwave PC version JMJS 09.3.30 2369
89  ncsim option example JMJS 08.12.1 4736
88  [영상]keywords for web search JMJS 08.12.1 2338
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6536
86  ncverilog option example JMJS 10.6.8 8195
85  [Verilog]Latch example JMJS 08.12.1 2934
84  Pad verilog example JMJS 01.3.16 4877
83  [ModelSim] vector JMJS 01.3.16 2553
82  RTL Code 분석순서 JMJS 09.4.29 2818
81  [temp]PIPE JMJS 08.10.2 2208
80  [temp]always-forever 무한루프 JMJS 08.10.2 2289
79  YCbCr2RGB.v JMJS 10.5.12 2483
78  [VHDL]rom64x8 JMJS 09.3.27 2047
77  [function]vector_compare JMJS 02.6.19 1948
76  [function]vector2integer JMJS 02.6.19 2127
75  [VHDL]ram8x4x8 JMJS 08.12.1 1903
74  [예]shift JMJS 02.6.19 2333
73  test JMJS 09.7.20 2164
72  test JMJS 09.7.20 1781
71  test JMJS 09.7.20 1884
70  test JMJS 09.7.20 1977
69  test JMJS 09.7.20 2022
68  test JMJS 09.7.20 1957
67  test JMJS 09.7.20 1890
66  test JMJS 09.7.20 1841
65  test JMJS 09.7.20 1947
64  test JMJS 09.7.20 2151
63  test JMJS 09.7.20 2186
62  test JMJS 09.7.20 2097
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3879
60  test JMJS 09.7.20 1718
59  test JMJS 09.7.20 1992
58  test JMJS 09.7.20 1922
57  test JMJS 09.7.20 1887
56  test JMJS 09.7.20 1926
55  verilog 학과 샘플강의 JMJS 16.5.30 2421
54  [verilog]create_generated_clock JMJS 15.4.28 2397
53  [Verilog]JDIFF JMJS 14.7.4 1742
52  [verilog]parameter definition JMJS 14.3.5 2037
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4970
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2666
49  Verdi JMJS 10.4.22 3507
48  draw hexa JMJS 10.4.9 2043
47  asfifo - Async FIFO JMJS 10.4.8 1907
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3582
45  synplify batch JMJS 10.3.8 2738
44  전자시계 Type A JMJS 08.11.28 2245
43  I2C Webpage JMJS 08.2.25 2083
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6220
41  [Verilog]vstring JMJS 17.9.27 2300
40  Riviera Simple Case JMJS 09.4.29 3388
39  [VHDL]DES Example JMJS 07.6.15 3233
38  [verilog]RAM example JMJS 09.6.5 3010
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2262
36  Jamie's VHDL Handbook JMJS 08.11.28 2923
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3527
34  RTL Job JMJS 09.4.29 2435
33  [VHDL]type example - package TYPES JMJS 06.2.2 1955
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9594
30  [verilog]array_module JMJS 05.12.8 2487
29  [verilog-2001]generate JMJS 05.12.8 3628
28  protected JMJS 05.11.18 2287
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3055
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2050
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2666
23  Array Of Array JMJS 04.8.16 2195
22  dumpfile, dumpvars JMJS 04.7.19 3868
21  Vending Machine Jamie 02.12.16 10306
20  Mini Vending Machine1 Jamie 02.12.10 7181
19  Mini Vending Machine Jamie 02.12.6 10028
18  Key Jamie 02.11.29 5202
17  Stop Watch Jamie 02.11.25 5799
16  Mealy Machine Jamie 02.8.29 6943
15  Moore Machine Jamie 02.8.29 18280
14  Up Down Counter Jamie 02.8.29 4300
13  Up Counter Jamie 02.8.29 2996
12  Edge Detecter Jamie 02.8.29 3216
11  Concept4 Jamie 02.8.28 2219
10  Concept3 Jamie 02.8.28 2285
9  Concept2_1 Jamie 02.8.28 2173
8  Concept2 Jamie 02.8.28 2262
7  Concept1 Jamie 02.8.26 2347
6  Tri State Buffer Jamie 02.8.26 3827
5  8x3 Encoder Jamie 02.8.28 4420
4  3x8 Decoder Jamie 02.8.28 4044
3  4bit Comparator Jamie 02.8.26 3433
2  가위 바위 보 게임 Jamie 02.8.26 5643
1  Two Input Logic Jamie 02.8.26 2677
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