library IEEE;
use IEEE.STD_Logic_1164.all;
use IEEE.STD_Logic_Unsigned.all;
entity ArrayOfArray is
end ArrayOfArray;
architecture JMJS_Logic of ArrayOfArray is
type yarray is array (0 to 15) of std_logic_vector (3 downto 0);
type xarray is array (0 to 15) of yarray;
signal xy : xarray;
signal adata : std_logic_vector (3 downto 0);
begin
process
variable bdata : std_logic_vector (3 downto 0) := "0000";
begin
for I in 0 to 15 loop
for J in 0 to 15 loop
xy(I)(J) <= bdata;
wait for 10 ns;
adata (2 downto 0) <= xy(I)(J)(3 downto 1);
bdata := bdata + "1";
end loop;
end loop;
end process;
end JMJS_Logic