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RTL Job
# 34 JMJS    09.4.29 07:43

sub tb design

sub design

dk manage

top design

top tb design

sim env make (short time, long time, regression test)
    run.f make

presim env make

postsim env make

top rtl sim

tv making

sdc making

synthesis

top pre sim

top post sim

power sim
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 340
97  test plusargs value plusargs JMJS 24.9.5 354
96  color text JMJS 24.7.13 399
95  draw_hexa.v JMJS 10.6.17 2552
94  jmjsxram3.v JMJS 10.4.9 2480
93  Verilog document JMJS 11.1.24 3075
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2668
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4103
90  gtkwave PC version JMJS 09.3.30 2489
89  ncsim option example JMJS 08.12.1 4837
88  [영상]keywords for web search JMJS 08.12.1 2447
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6559
86  ncverilog option example JMJS 10.6.8 8298
85  [Verilog]Latch example JMJS 08.12.1 3039
84  Pad verilog example JMJS 01.3.16 4988
83  [ModelSim] vector JMJS 01.3.16 2670
82  RTL Code 분석순서 JMJS 09.4.29 2906
81  [temp]PIPE JMJS 08.10.2 2311
80  [temp]always-forever 무한루프 JMJS 08.10.2 2391
79  YCbCr2RGB.v JMJS 10.5.12 2574
78  [VHDL]rom64x8 JMJS 09.3.27 2119
77  [function]vector_compare JMJS 02.6.19 2001
76  [function]vector2integer JMJS 02.6.19 2235
75  [VHDL]ram8x4x8 JMJS 08.12.1 1947
74  [예]shift JMJS 02.6.19 2418
73  test JMJS 09.7.20 2278
72  test JMJS 09.7.20 1801
71  test JMJS 09.7.20 1992
70  test JMJS 09.7.20 2079
69  test JMJS 09.7.20 2131
68  test JMJS 09.7.20 2072
67  test JMJS 09.7.20 2001
66  test JMJS 09.7.20 1943
65  test JMJS 09.7.20 2071
64  test JMJS 09.7.20 2258
63  test JMJS 09.7.20 2304
62  test JMJS 09.7.20 2183
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3965
60  test JMJS 09.7.20 1729
59  test JMJS 09.7.20 2113
58  test JMJS 09.7.20 2023
57  test JMJS 09.7.20 1986
56  test JMJS 09.7.20 2024
55  verilog 학과 샘플강의 JMJS 16.5.30 2439
54  [verilog]create_generated_clock JMJS 15.4.28 2433
53  [Verilog]JDIFF JMJS 14.7.4 1866
52  [verilog]parameter definition JMJS 14.3.5 2134
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5080
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2705
49  Verdi JMJS 10.4.22 3626
48  draw hexa JMJS 10.4.9 2095
47  asfifo - Async FIFO JMJS 10.4.8 1958
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3645
45  synplify batch JMJS 10.3.8 2851
44  전자시계 Type A JMJS 08.11.28 2352
43  I2C Webpage JMJS 08.2.25 2178
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6256
41  [Verilog]vstring JMJS 17.9.27 2372
40  Riviera Simple Case JMJS 09.4.29 3457
39  [VHDL]DES Example JMJS 07.6.15 3344
38  [verilog]RAM example JMJS 09.6.5 3104
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2349
36  Jamie's VHDL Handbook JMJS 08.11.28 3047
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3626
34  RTL Job JMJS 09.4.29 2563
33  [VHDL]type example - package TYPES JMJS 06.2.2 1987
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9682
30  [verilog]array_module JMJS 05.12.8 2587
29  [verilog-2001]generate JMJS 05.12.8 3732
28  protected JMJS 05.11.18 2402
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3118
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2097
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2731
23  Array Of Array JMJS 04.8.16 2273
22  dumpfile, dumpvars JMJS 04.7.19 3975
21  Vending Machine Jamie 02.12.16 10412
20  Mini Vending Machine1 Jamie 02.12.10 7262
19  Mini Vending Machine Jamie 02.12.6 10097
18  Key Jamie 02.11.29 5310
17  Stop Watch Jamie 02.11.25 5830
16  Mealy Machine Jamie 02.8.29 7038
15  Moore Machine Jamie 02.8.29 18373
14  Up Down Counter Jamie 02.8.29 4405
13  Up Counter Jamie 02.8.29 3098
12  Edge Detecter Jamie 02.8.29 3310
11  Concept4 Jamie 02.8.28 2243
10  Concept3 Jamie 02.8.28 2367
9  Concept2_1 Jamie 02.8.28 2266
8  Concept2 Jamie 02.8.28 2352
7  Concept1 Jamie 02.8.26 2360
6  Tri State Buffer Jamie 02.8.26 3960
5  8x3 Encoder Jamie 02.8.28 4503
4  3x8 Decoder Jamie 02.8.28 4137
3  4bit Comparator Jamie 02.8.26 3513
2  가위 바위 보 게임 Jamie 02.8.26 5656
1  Two Input Logic Jamie 02.8.26 2774
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