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# 34

JMJS 09.4.29 07:43

sub tb design

sub design

dk manage

top design

top tb design

sim env make (short time, long time, regression test)
run.f make

presim env make

postsim env make

top rtl sim

tv making

sdc making

synthesis

top pre sim

top post sim

power sim

게시물: 96 건, 현재: 1 / 1 쪽
번호	제 목	작성자	등록일	방문
98	interface	JMJS	25.1.20	236
97	test plusargs value plusargs	JMJS	24.9.5	288
96	color text	JMJS	24.7.13	289
95	draw_hexa.v	JMJS	10.6.17	2496
94	jmjsxram3.v	JMJS	10.4.9	2255
93	Verilog document	JMJS	11.1.24	2867
92	[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;	JMJS	09.3.31	2457
91	[verilog]forever, repeat, strobe, realtime, ...	JMJS	09.7.6	3875
90	gtkwave PC version	JMJS	09.3.30	2216
89	ncsim option example	JMJS	08.12.1	4600
88	[영상]keywords for web search	JMJS	08.12.1	2225
87	[Verilog]fdisplay fopen fscanf	JMJS	11.1.24	6484
86	ncverilog option example	JMJS	10.6.8	8066
85	[Verilog]Latch example	JMJS	08.12.1	2814
84	Pad verilog example	JMJS	01.3.16	4723
83	[ModelSim] vector	JMJS	01.3.16	2422
82	RTL Code 분석순서	JMJS	09.4.29	2708
81	[temp]PIPE	JMJS	08.10.2	2074
80	[temp]always-forever 무한루프	JMJS	08.10.2	2166
79	YCbCr2RGB.v	JMJS	10.5.12	2357
78	[VHDL]rom64x8	JMJS	09.3.27	1949
77	[function]vector_compare	JMJS	02.6.19	1859
76	[function]vector2integer	JMJS	02.6.19	1986
75	[VHDL]ram8x4x8	JMJS	08.12.1	1838
74	[예]shift	JMJS	02.6.19	2240
73	test	JMJS	09.7.20	2031
72	test	JMJS	09.7.20	1751
71	test	JMJS	09.7.20	1743
70	test	JMJS	09.7.20	1836
69	test	JMJS	09.7.20	1883
68	test	JMJS	09.7.20	1828
67	test	JMJS	09.7.20	1746
66	test	JMJS	09.7.20	1729
65	test	JMJS	09.7.20	1818
64	test	JMJS	09.7.20	2026
63	test	JMJS	09.7.20	2046
62	test	JMJS	09.7.20	1970
61	VHDL의 연산자 우선순위	JMJS	09.7.20	3767
60	test	JMJS	09.7.20	1683
59	test	JMJS	09.7.20	1839
58	test	JMJS	09.7.20	1813
57	test	JMJS	09.7.20	1766
56	test	JMJS	09.7.20	1818
55	verilog 학과 샘플강의	JMJS	16.5.30	2371
54	[verilog]create_generated_clock	JMJS	15.4.28	2344
53	[Verilog]JDIFF	JMJS	14.7.4	1616
52	[verilog]parameter definition	JMJS	14.3.5	1918
51	[verilog]sformat fopen fscanf fwrite fclose	JMJS	12.1.31	4871
50	Verilog File I/0,Verilog file handling	JMJS	12.1.30	2609
49	Verdi	JMJS	10.4.22	3379
48	draw hexa	JMJS	10.4.9	1970
47	asfifo - Async FIFO	JMJS	10.4.8	1833
46	VHDL을 이용한 회로설계의 장점	JMJS	02.3.14	3489
45	synplify batch	JMJS	10.3.8	2599
44	전자시계 Type A	JMJS	08.11.28	2119
43	I2C Webpage	JMJS	08.2.25	1960
42	PC에서 간단히 Verilog 실행해보기 (Icarus Verilog)	JMJS	13.1.14	6108
41	[Verilog]vstring	JMJS	17.9.27	2184
40	Riviera Simple Case	JMJS	09.4.29	3305
39	[VHDL]DES Example	JMJS	07.6.15	3102
38	[verilog]RAM example	JMJS	09.6.5	2861
37	ROM example [VerilogHDL, RTL]	JMJS	04.5.27	2143
36	Jamie's VHDL Handbook	JMJS	08.11.28	2809
35	Dualport RAM example [VerilogHDL, RTL]	JMJS	04.5.27	3426
34	RTL Job	JMJS	09.4.29	2273
33	[VHDL]type example - package TYPES	JMJS	06.2.2	1894
32	[verilog]`define `ifdef `elsif `else `endif ...	JMJS	10.5.11	9474
30	[verilog]array_module	JMJS	05.12.8	2403
29	[verilog-2001]generate	JMJS	05.12.8	3507
28	protected	JMJS	05.11.18	2169
27	design에 latch가 있으면 안되나요?	JMJS	09.7.20	2965
26	bus의 데이타를 각 bit별로 출력하는 방법은?	JMJS	04.11.9	1951
25	component를 생성해서 다른 곳에서 호출하는 방법	JMJS	04.11.4	2593
23	Array Of Array	JMJS	04.8.16	2106
22	dumpfile, dumpvars	JMJS	04.7.19	3730
21	Vending Machine	Jamie	02.12.16	10187
20	Mini Vending Machine1	Jamie	02.12.10	7073
19	Mini Vending Machine	Jamie	02.12.6	9927
18	Key	Jamie	02.11.29	5083
17	Stop Watch	Jamie	02.11.25	5736
16	Mealy Machine	Jamie	02.8.29	6835
15	Moore Machine	Jamie	02.8.29	18140
14	Up Down Counter	Jamie	02.8.29	4177
13	Up Counter	Jamie	02.8.29	2865
12	Edge Detecter	Jamie	02.8.29	3094
11	Concept4	Jamie	02.8.28	2161
10	Concept3	Jamie	02.8.28	2185
9	Concept2_1	Jamie	02.8.28	2066
8	Concept2	Jamie	02.8.28	2161
7	Concept1	Jamie	02.8.26	2316
6	Tri State Buffer	Jamie	02.8.26	3668
5	8x3 Encoder	Jamie	02.8.28	4286
4	3x8 Decoder	Jamie	02.8.28	3940
3	4bit Comparator	Jamie	02.8.26	3321
2	가위 바위 보 게임	Jamie	02.8.26	5609
1	Two Input Logic	Jamie	02.8.26	2572

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