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RTL Job
# 34 JMJS    09.4.29 07:43

sub tb design

sub design

dk manage

top design

top tb design

sim env make (short time, long time, regression test)
    run.f make

presim env make

postsim env make

top rtl sim

tv making

sdc making

synthesis

top pre sim

top post sim

power sim

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1879
94  jmjsxram3.v JMJS 10.4.9 1664
93  Verilog document JMJS 11.1.24 2224
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1798
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3240
90  gtkwave PC version JMJS 09.3.30 1625
89  ncsim option example JMJS 08.12.1 3922
88  [영상]keywords for web search JMJS 08.12.1 1610
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5878
86  ncverilog option example JMJS 10.6.8 7196
85  [Verilog]Latch example JMJS 08.12.1 2236
84  Pad verilog example JMJS 01.3.16 4113
83  [ModelSim] vector JMJS 01.3.16 1818
82  RTL Code 분석순서 JMJS 09.4.29 2103
81  [temp]PIPE JMJS 08.10.2 1515
80  [temp]always-forever 무한루프 JMJS 08.10.2 1564
79  YCbCr2RGB.v JMJS 10.5.12 1763
78  [VHDL]rom64x8 JMJS 09.3.27 1383
77  [function]vector_compare JMJS 02.6.19 1330
76  [function]vector2integer JMJS 02.6.19 1432
75  [VHDL]ram8x4x8 JMJS 08.12.1 1314
74  [예]shift JMJS 02.6.19 1632
73  test JMJS 09.7.20 1418
72  test JMJS 09.7.20 1255
71  test JMJS 09.7.20 1174
70  test JMJS 09.7.20 1306
69  test JMJS 09.7.20 1327
68  test JMJS 09.7.20 1232
67  test JMJS 09.7.20 1155
66  test JMJS 09.7.20 1135
65  test JMJS 09.7.20 1238
64  test JMJS 09.7.20 1461
63  test JMJS 09.7.20 1458
62  test JMJS 09.7.20 1385
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3109
60  test JMJS 09.7.20 1160
59  test JMJS 09.7.20 1241
58  test JMJS 09.7.20 1254
57  test JMJS 09.7.20 1194
56  test JMJS 09.7.20 1265
55  verilog 학과 샘플강의 JMJS 16.5.30 1788
54  [verilog]create_generated_clock JMJS 15.4.28 1789
53  [Verilog]JDIFF JMJS 14.7.4 1130
52  [verilog]parameter definition JMJS 14.3.5 1388
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4200
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2075
49  Verdi JMJS 10.4.22 2619
48  draw hexa JMJS 10.4.9 1459
47  asfifo - Async FIFO JMJS 10.4.8 1290
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2889
45  synplify batch JMJS 10.3.8 2029
44  전자시계 Type A JMJS 08.11.28 1543
43  I2C Webpage JMJS 08.2.25 1404
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5323
41  [Verilog]vstring JMJS 17.9.27 1660
40  Riviera Simple Case JMJS 09.4.29 2749
39  [VHDL]DES Example JMJS 07.6.15 2522
38  [verilog]RAM example JMJS 09.6.5 2300
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1583
36  Jamie's VHDL Handbook JMJS 08.11.28 2207
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2829
34  RTL Job JMJS 09.4.29 1682
33  [VHDL]type example - package TYPES JMJS 06.2.2 1370
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8720
30  [verilog]array_module JMJS 05.12.8 1729
29  [verilog-2001]generate JMJS 05.12.8 2931
28  protected JMJS 05.11.18 1570
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2404
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1502
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2003
23  Array Of Array JMJS 04.8.16 1584
22  dumpfile, dumpvars JMJS 04.7.19 3160
21  Vending Machine Jamie 02.12.16 9539
20  Mini Vending Machine1 Jamie 02.12.10 6382
19  Mini Vending Machine Jamie 02.12.6 9185
18  Key Jamie 02.11.29 4506
17  Stop Watch Jamie 02.11.25 5245
16  Mealy Machine Jamie 02.8.29 6076
15  Moore Machine Jamie 02.8.29 16374
14  Up Down Counter Jamie 02.8.29 3515
13  Up Counter Jamie 02.8.29 2315
12  Edge Detecter Jamie 02.8.29 2484
11  Concept4 Jamie 02.8.28 1642
10  Concept3 Jamie 02.8.28 1640
9  Concept2_1 Jamie 02.8.28 1504
8  Concept2 Jamie 02.8.28 1601
7  Concept1 Jamie 02.8.26 1790
6  Tri State Buffer Jamie 02.8.26 3060
5  8x3 Encoder Jamie 02.8.28 3641
4  3x8 Decoder Jamie 02.8.28 3340
3  4bit Comparator Jamie 02.8.26 2752
2  가위 바위 보 게임 Jamie 02.8.26 5045
1  Two Input Logic Jamie 02.8.26 2041
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