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RTL Job
# 34 JMJS    09.4.29 07:43

sub tb design

sub design

dk manage

top design

top tb design

sim env make (short time, long time, regression test)
    run.f make

presim env make

postsim env make

top rtl sim

tv making

sdc making

synthesis

top pre sim

top post sim

power sim

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1857
94  jmjsxram3.v JMJS 10.4.9 1639
93  Verilog document JMJS 11.1.24 2200
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1779
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3217
90  gtkwave PC version JMJS 09.3.30 1606
89  ncsim option example JMJS 08.12.1 3886
88  [영상]keywords for web search JMJS 08.12.1 1589
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5847
86  ncverilog option example JMJS 10.6.8 7133
85  [Verilog]Latch example JMJS 08.12.1 2213
84  Pad verilog example JMJS 01.3.16 4082
83  [ModelSim] vector JMJS 01.3.16 1801
82  RTL Code 분석순서 JMJS 09.4.29 2077
81  [temp]PIPE JMJS 08.10.2 1496
80  [temp]always-forever 무한루프 JMJS 08.10.2 1543
79  YCbCr2RGB.v JMJS 10.5.12 1742
78  [VHDL]rom64x8 JMJS 09.3.27 1368
77  [function]vector_compare JMJS 02.6.19 1311
76  [function]vector2integer JMJS 02.6.19 1412
75  [VHDL]ram8x4x8 JMJS 08.12.1 1296
74  [예]shift JMJS 02.6.19 1612
73  test JMJS 09.7.20 1400
72  test JMJS 09.7.20 1239
71  test JMJS 09.7.20 1157
70  test JMJS 09.7.20 1290
69  test JMJS 09.7.20 1311
68  test JMJS 09.7.20 1218
67  test JMJS 09.7.20 1141
66  test JMJS 09.7.20 1117
65  test JMJS 09.7.20 1218
64  test JMJS 09.7.20 1426
63  test JMJS 09.7.20 1421
62  test JMJS 09.7.20 1346
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3063
60  test JMJS 09.7.20 1139
59  test JMJS 09.7.20 1220
58  test JMJS 09.7.20 1233
57  test JMJS 09.7.20 1174
56  test JMJS 09.7.20 1248
55  verilog 학과 샘플강의 JMJS 16.5.30 1705
54  [verilog]create_generated_clock JMJS 15.4.28 1750
53  [Verilog]JDIFF JMJS 14.7.4 1113
52  [verilog]parameter definition JMJS 14.3.5 1373
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4114
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2050
49  Verdi JMJS 10.4.22 2595
48  draw hexa JMJS 10.4.9 1441
47  asfifo - Async FIFO JMJS 10.4.8 1268
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2861
45  synplify batch JMJS 10.3.8 2008
44  전자시계 Type A JMJS 08.11.28 1513
43  I2C Webpage JMJS 08.2.25 1392
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5252
41  [Verilog]vstring JMJS 17.9.27 1647
40  Riviera Simple Case JMJS 09.4.29 2703
39  [VHDL]DES Example JMJS 07.6.15 2511
38  [verilog]RAM example JMJS 09.6.5 2285
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1570
36  Jamie's VHDL Handbook JMJS 08.11.28 2193
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2815
34  RTL Job JMJS 09.4.29 1667
33  [VHDL]type example - package TYPES JMJS 06.2.2 1354
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8622
30  [verilog]array_module JMJS 05.12.8 1699
29  [verilog-2001]generate JMJS 05.12.8 2917
28  protected JMJS 05.11.18 1551
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2377
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1484
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 1977
23  Array Of Array JMJS 04.8.16 1570
22  dumpfile, dumpvars JMJS 04.7.19 3128
21  Vending Machine Jamie 02.12.16 9461
20  Mini Vending Machine1 Jamie 02.12.10 6315
19  Mini Vending Machine Jamie 02.12.6 9085
18  Key Jamie 02.11.29 4464
17  Stop Watch Jamie 02.11.25 5205
16  Mealy Machine Jamie 02.8.29 6012
15  Moore Machine Jamie 02.8.29 16208
14  Up Down Counter Jamie 02.8.29 3474
13  Up Counter Jamie 02.8.29 2297
12  Edge Detecter Jamie 02.8.29 2457
11  Concept4 Jamie 02.8.28 1626
10  Concept3 Jamie 02.8.28 1621
9  Concept2_1 Jamie 02.8.28 1492
8  Concept2 Jamie 02.8.28 1584
7  Concept1 Jamie 02.8.26 1774
6  Tri State Buffer Jamie 02.8.26 3041
5  8x3 Encoder Jamie 02.8.28 3590
4  3x8 Decoder Jamie 02.8.28 3303
3  4bit Comparator Jamie 02.8.26 2719
2  가위 바위 보 게임 Jamie 02.8.26 4937
1  Two Input Logic Jamie 02.8.26 2022
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