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사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2001 94  jmjsxram3.v JMJS 10.4.9 1734 93  Verilog document JMJS 11.1.24 2329 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1903 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3382 90  gtkwave PC version JMJS 09.3.30 1699 89  ncsim option example JMJS 08.12.1 4084 88  [영상]keywords for web search JMJS 08.12.1 1719 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6040 86  ncverilog option example JMJS 10.6.8 7403 85  [Verilog]Latch example JMJS 08.12.1 2322 84  Pad verilog example JMJS 01.3.16 4238 83  [ModelSim] vector JMJS 01.3.16 1931 82  RTL Code 분석순서 JMJS 09.4.29 2220 81  [temp]PIPE JMJS 08.10.2 1590 80  [temp]always-forever 무한루프 JMJS 08.10.2 1654 79  YCbCr2RGB.v JMJS 10.5.12 1873 78  [VHDL]rom64x8 JMJS 09.3.27 1487 77  [function]vector_compare JMJS 02.6.19 1450 76  [function]vector2integer JMJS 02.6.19 1516 75  [VHDL]ram8x4x8 JMJS 08.12.1 1392 74  [예]shift JMJS 02.6.19 1751 73  test JMJS 09.7.20 1520 72  test JMJS 09.7.20 1335 71  test JMJS 09.7.20 1269 70  test JMJS 09.7.20 1376 69  test JMJS 09.7.20 1411 68  test JMJS 09.7.20 1333 67  test JMJS 09.7.20 1247 66  test JMJS 09.7.20 1213 65  test JMJS 09.7.20 1321 64  test JMJS 09.7.20 1587 63  test JMJS 09.7.20 1578 62  test JMJS 09.7.20 1509 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3313 60  test JMJS 09.7.20 1240 59  test JMJS 09.7.20 1329 58  test JMJS 09.7.20 1357 57  test JMJS 09.7.20 1292 56  test JMJS 09.7.20 1338 55  verilog 학과 샘플강의 JMJS 16.5.30 1964 54  [verilog]create_generated_clock JMJS 15.4.28 1925 53  [Verilog]JDIFF JMJS 14.7.4 1209 52  [verilog]parameter definition JMJS 14.3.5 1464 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4377 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2193 49  Verdi JMJS 10.4.22 2770 48  draw hexa JMJS 10.4.9 1549 47  asfifo - Async FIFO JMJS 10.4.8 1384 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3019 45  synplify batch JMJS 10.3.8 2134 44  전자시계 Type A JMJS 08.11.28 1636 43  I2C Webpage JMJS 08.2.25 1506 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5732 41  [Verilog]vstring JMJS 17.9.27 1737 40  Riviera Simple Case JMJS 09.4.29 2881 39  [VHDL]DES Example JMJS 07.6.15 2617 38  [verilog]RAM example JMJS 09.6.5 2410 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1659 36  Jamie's VHDL Handbook JMJS 08.11.28 2308 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2929 34  RTL Job JMJS 09.4.29 1774 33  [VHDL]type example - package TYPES JMJS 06.2.2 1469 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9050 30  [verilog]array_module JMJS 05.12.8 1850 29  [verilog-2001]generate JMJS 05.12.8 3046 28  protected JMJS 05.11.18 1671 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2505 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1569 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2116 23  Array Of Array JMJS 04.8.16 1659 22  dumpfile, dumpvars JMJS 04.7.19 3299 21  Vending Machine Jamie 02.12.16 9776 20  Mini Vending Machine1 Jamie 02.12.10 6562 19  Mini Vending Machine Jamie 02.12.6 9432 18  Key Jamie 02.11.29 4650 17  Stop Watch Jamie 02.11.25 5362 16  Mealy Machine Jamie 02.8.29 6339 15  Moore Machine Jamie 02.8.29 16833 14  Up Down Counter Jamie 02.8.29 3649 13  Up Counter Jamie 02.8.29 2430 12  Edge Detecter Jamie 02.8.29 2630 11  Concept4 Jamie 02.8.28 1767 10  Concept3 Jamie 02.8.28 1727 9  Concept2_1 Jamie 02.8.28 1611 8  Concept2 Jamie 02.8.28 1689 7  Concept1 Jamie 02.8.26 1893 6  Tri State Buffer Jamie 02.8.26 3202 5  8x3 Encoder Jamie 02.8.28 3799 4  3x8 Decoder Jamie 02.8.28 3490 3  4bit Comparator Jamie 02.8.26 2856 2  가위 바위 보 게임 Jamie 02.8.26 5232 1  Two Input Logic Jamie 02.8.26 2124 [1]