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사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 [1] 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2074 94  jmjsxram3.v JMJS 10.4.9 1814 93  Verilog document JMJS 11.1.24 2404 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1957 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3451 90  gtkwave PC version JMJS 09.3.30 1746 89  ncsim option example JMJS 08.12.1 4147 88  [영상]keywords for web search JMJS 08.12.1 1784 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6146 86  ncverilog option example JMJS 10.6.8 7534 85  [Verilog]Latch example JMJS 08.12.1 2366 84  Pad verilog example JMJS 01.3.16 4314 83  [ModelSim] vector JMJS 01.3.16 1977 82  RTL Code 분석순서 JMJS 09.4.29 2271 81  [temp]PIPE JMJS 08.10.2 1649 80  [temp]always-forever 무한루프 JMJS 08.10.2 1712 79  YCbCr2RGB.v JMJS 10.5.12 1931 78  [VHDL]rom64x8 JMJS 09.3.27 1537 77  [function]vector_compare JMJS 02.6.19 1506 76  [function]vector2integer JMJS 02.6.19 1577 75  [VHDL]ram8x4x8 JMJS 08.12.1 1441 74  [예]shift JMJS 02.6.19 1815 73  test JMJS 09.7.20 1569 72  test JMJS 09.7.20 1388 71  test JMJS 09.7.20 1335 70  test JMJS 09.7.20 1424 69  test JMJS 09.7.20 1459 68  test JMJS 09.7.20 1387 67  test JMJS 09.7.20 1300 66  test JMJS 09.7.20 1276 65  test JMJS 09.7.20 1366 64  test JMJS 09.7.20 1645 63  test JMJS 09.7.20 1635 62  test JMJS 09.7.20 1558 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3451 60  test JMJS 09.7.20 1293 59  test JMJS 09.7.20 1387 58  test JMJS 09.7.20 1419 57  test JMJS 09.7.20 1336 56  test JMJS 09.7.20 1384 55  verilog 학과 샘플강의 JMJS 16.5.30 2080 54  [verilog]create_generated_clock JMJS 15.4.28 1995 53  [Verilog]JDIFF JMJS 14.7.4 1256 52  [verilog]parameter definition JMJS 14.3.5 1511 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4486 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2247 49  Verdi JMJS 10.4.22 2910 48  draw hexa JMJS 10.4.9 1600 47  asfifo - Async FIFO JMJS 10.4.8 1425 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3104 45  synplify batch JMJS 10.3.8 2187 44  전자시계 Type A JMJS 08.11.28 1683 43  I2C Webpage JMJS 08.2.25 1552 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5963 41  [Verilog]vstring JMJS 17.9.27 1790 40  Riviera Simple Case JMJS 09.4.29 2971 39  [VHDL]DES Example JMJS 07.6.15 2671 38  [verilog]RAM example JMJS 09.6.5 2467 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1691 36  Jamie's VHDL Handbook JMJS 08.11.28 2348 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2978 34  RTL Job JMJS 09.4.29 1834 33  [VHDL]type example - package TYPES JMJS 06.2.2 1526 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9487 30  [verilog]array_module JMJS 05.12.8 1908 29  [verilog-2001]generate JMJS 05.12.8 3143 28  protected JMJS 05.11.18 1724 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2570 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1608 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2163 23  Array Of Array JMJS 04.8.16 1732 22  dumpfile, dumpvars JMJS 04.7.19 3360 21  Vending Machine Jamie 02.12.16 9934 20  Mini Vending Machine1 Jamie 02.12.10 6679 19  Mini Vending Machine Jamie 02.12.6 9588 18  Key Jamie 02.11.29 4729 17  Stop Watch Jamie 02.11.25 5448 16  Mealy Machine Jamie 02.8.29 6503 15  Moore Machine Jamie 02.8.29 17185 14  Up Down Counter Jamie 02.8.29 3737 13  Up Counter Jamie 02.8.29 2466 12  Edge Detecter Jamie 02.8.29 2717 11  Concept4 Jamie 02.8.28 1812 10  Concept3 Jamie 02.8.28 1769 9  Concept2_1 Jamie 02.8.28 1664 8  Concept2 Jamie 02.8.28 1735 7  Concept1 Jamie 02.8.26 1956 6  Tri State Buffer Jamie 02.8.26 3260 5  8x3 Encoder Jamie 02.8.28 3903 4  3x8 Decoder Jamie 02.8.28 3592 3  4bit Comparator Jamie 02.8.26 2936 2  가위 바위 보 게임 Jamie 02.8.26 5348 1  Two Input Logic Jamie 02.8.26 2181 [1]