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사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 [1] 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2094 94  jmjsxram3.v JMJS 10.4.9 1828 93  Verilog document JMJS 11.1.24 2416 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1976 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3463 90  gtkwave PC version JMJS 09.3.30 1760 89  ncsim option example JMJS 08.12.1 4161 88  [영상]keywords for web search JMJS 08.12.1 1798 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6163 86  ncverilog option example JMJS 10.6.8 7552 85  [Verilog]Latch example JMJS 08.12.1 2378 84  Pad verilog example JMJS 01.3.16 4335 83  [ModelSim] vector JMJS 01.3.16 1990 82  RTL Code 분석순서 JMJS 09.4.29 2287 81  [temp]PIPE JMJS 08.10.2 1661 80  [temp]always-forever 무한루프 JMJS 08.10.2 1722 79  YCbCr2RGB.v JMJS 10.5.12 1944 78  [VHDL]rom64x8 JMJS 09.3.27 1549 77  [function]vector_compare JMJS 02.6.19 1517 76  [function]vector2integer JMJS 02.6.19 1585 75  [VHDL]ram8x4x8 JMJS 08.12.1 1451 74  [예]shift JMJS 02.6.19 1826 73  test JMJS 09.7.20 1581 72  test JMJS 09.7.20 1403 71  test JMJS 09.7.20 1349 70  test JMJS 09.7.20 1436 69  test JMJS 09.7.20 1471 68  test JMJS 09.7.20 1399 67  test JMJS 09.7.20 1316 66  test JMJS 09.7.20 1284 65  test JMJS 09.7.20 1378 64  test JMJS 09.7.20 1656 63  test JMJS 09.7.20 1645 62  test JMJS 09.7.20 1569 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3488 60  test JMJS 09.7.20 1301 59  test JMJS 09.7.20 1397 58  test JMJS 09.7.20 1432 57  test JMJS 09.7.20 1351 56  test JMJS 09.7.20 1395 55  verilog 학과 샘플강의 JMJS 16.5.30 2103 54  [verilog]create_generated_clock JMJS 15.4.28 2006 53  [Verilog]JDIFF JMJS 14.7.4 1272 52  [verilog]parameter definition JMJS 14.3.5 1522 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4505 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2260 49  Verdi JMJS 10.4.22 2933 48  draw hexa JMJS 10.4.9 1613 47  asfifo - Async FIFO JMJS 10.4.8 1437 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3117 45  synplify batch JMJS 10.3.8 2198 44  전자시계 Type A JMJS 08.11.28 1695 43  I2C Webpage JMJS 08.2.25 1562 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5991 41  [Verilog]vstring JMJS 17.9.27 1803 40  Riviera Simple Case JMJS 09.4.29 2984 39  [VHDL]DES Example JMJS 07.6.15 2686 38  [verilog]RAM example JMJS 09.6.5 2479 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1703 36  Jamie's VHDL Handbook JMJS 08.11.28 2357 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2987 34  RTL Job JMJS 09.4.29 1844 33  [VHDL]type example - package TYPES JMJS 06.2.2 1537 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9534 30  [verilog]array_module JMJS 05.12.8 1918 29  [verilog-2001]generate JMJS 05.12.8 3156 28  protected JMJS 05.11.18 1734 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2581 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1620 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2172 23  Array Of Array JMJS 04.8.16 1742 22  dumpfile, dumpvars JMJS 04.7.19 3371 21  Vending Machine Jamie 02.12.16 9979 20  Mini Vending Machine1 Jamie 02.12.10 6703 19  Mini Vending Machine Jamie 02.12.6 9633 18  Key Jamie 02.11.29 4747 17  Stop Watch Jamie 02.11.25 5467 16  Mealy Machine Jamie 02.8.29 6527 15  Moore Machine Jamie 02.8.29 17231 14  Up Down Counter Jamie 02.8.29 3753 13  Up Counter Jamie 02.8.29 2476 12  Edge Detecter Jamie 02.8.29 2736 11  Concept4 Jamie 02.8.28 1823 10  Concept3 Jamie 02.8.28 1778 9  Concept2_1 Jamie 02.8.28 1676 8  Concept2 Jamie 02.8.28 1744 7  Concept1 Jamie 02.8.26 1970 6  Tri State Buffer Jamie 02.8.26 3272 5  8x3 Encoder Jamie 02.8.28 3921 4  3x8 Decoder Jamie 02.8.28 3607 3  4bit Comparator Jamie 02.8.26 2963 2  가위 바위 보 게임 Jamie 02.8.26 5373 1  Two Input Logic Jamie 02.8.26 2192 [1]