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[verilog]create_generated_clock
# 54 JMJS    15.4.28 17:29

set target_clock_period_0    10.00
set shrink_ratio         1.00
set clock_period_0    [expr ${target_clock_period_0} * ${shrink_ratio}]

create_clock -name ACLK  -period $clock_period_0 [get_ports ACLK]
create_generated_clock -name ACLK2 -source [get_ports ACLK] -divide_by 2 [get_ports ACLK2]

  Startpoint: DATA0_reg[0]              (rising edge-triggered flip-flop clocked by ACLK)
  Endpoint: DATA2_reg[0]            (rising edge-triggered flip-flop clocked by ACLK)
   --------------------------------------------------------------------------
  clock ACLK (rise edge)                                0.0000     0.0000
  clock network delay (ideal)                           0.0000     0.0000
  DATA0_reg[0]/CK (SDFFRPQ_X1M_A9TL_C34)                0.0000     0.0000 r

  Startpoint: DATA1_reg[0]              (rising edge-triggered flip-flop clocked by ACLK2)
  Endpoint: DATA3_reg[0]            (rising edge-triggered flip-flop clocked by ACLK2)
  --------------------------------------------------------------------------
  clock ACLK2 (rise edge)                               0.0000     0.0000
  clock network delay (ideal)                           0.0000     0.0000
  DATA1_reg[0]/CK (SDFFRPQ_X1M_A9TL_C34)                0.0000     0.0000 r

  Startpoint: DATA4_reg[0]              (rising edge-triggered flip-flop clocked by ACLK)
  Endpoint: oDATA[0]                   (output port clocked by ACLK2)
  --------------------------------------------------------------------------
  clock ACLK (rise edge)                               10.0000    10.0000
  clock network delay (ideal)                           0.0000    10.0000
  DATA4_reg[0]/CK (SDFFRPQ_X1M_A9TL_C34)                0.0000    10.0000 r

create_generated_clock

Create clock

create_clock -name $clock_name -p $clock_period -w [list 0 $half_period] [get_ports $clock_pin]

create_clock -name $clock_name -p $clock_period -w [list 0 $half_period] [get_pins $clock_pin]

create_generated_clock -name $clock_name -source [get_ports $mclock_name] -divided_by $div [get_pins $clock_pin]

create_generated_clock -name $clock_name -source [get_pins $mclock_name] -divided_by $div [get_pins $clock_pin]


#Constrain the base clock

create_clock -add -period 10.000 \
-waveform { 0.000 5.000 } \
-name clock_name \
[get_ports clock]

#Constrain the output clock clock

create_generated_clock -add -source PLL_inst|inclk[0] \
-name PLL_inst|clk[1] \
-multiply_by 2 \
-master_clock clock_name \
[get_pins PLL_inst|clk[1]]

# Create a virtual clock to describe the data clock in
# the external device
create_clock -name virt_clk -period 10

# Create a base clock on the input port of the FPGA, with a 10 ns period
create_clock -name input_clock -period 10 [get_ports clk_in]

# Create generated clocks on the PLL outputs
create_generated_clock -name data_clock -source [get_pins pll|inclk[0]] \
-phase 90 [get_pins pll|clk[0]]

# Add maximum and minimum input delay constraints
# assuming a skew requirement of +/- 250ps
# Use the equations for the input delay values listed above
set_input_delay -max -clock virt_clk 0.250 [get_ports data_in*]
set_input_delay -min -clock virt_clk -0.250 [get_ports data_in*]
set_input_delay -max -clock virt_clk -clock_fall \
0.250 [get_ports data_in*] -add
set_input_delay -min -clock virt_clk -clock_fall \
-0.250 [get_ports data_in*] -add

# Add false path exceptions for cross-clock transfers
set_false_path -setup -end -rise_from [get_clocks virt_clk] \
-fall_to [get_clocks data_clock]
set_false_path -setup -end -fall_from [get_clocks virt_clk] \
-rise_to [get_clocks data_clock]
set_false_path -hold -end -rise_from [get_clocks virt_clk] \
-rise_to [get_clocks data_clock]
set_false_path -hold -end -fall_from [get_clocks virt_clk] \
-fall_to [get_clocks data_clock]

첨부파일: SYN_CG_tar.gz
게시물: 93 건, 현재: 1 / 1 쪽
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