LogIn E-mail
설계이야기
사과장수 
Study-HDL 
Script Tip 
Perl Tip 
C Memo 
Python 
[Verilog]Latch example
# 85 JMJS    08.12.1 14:11

always @(a,b)
        case(a)
        2'd1: c<=b+1;
        default: c<=c;
endcase
게시물: 93 건, 현재: 1 / 1 쪽
[1]
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2091
94  jmjsxram3.v JMJS 10.4.9 1825
93  Verilog document JMJS 11.1.24 2414
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1972
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3461
90  gtkwave PC version JMJS 09.3.30 1757
89  ncsim option example JMJS 08.12.1 4158
88  [영상]keywords for web search JMJS 08.12.1 1796
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6162
86  ncverilog option example JMJS 10.6.8 7550
85  [Verilog]Latch example JMJS 08.12.1 2376
84  Pad verilog example JMJS 01.3.16 4332
83  [ModelSim] vector JMJS 01.3.16 1987
82  RTL Code 분석순서 JMJS 09.4.29 2284
81  [temp]PIPE JMJS 08.10.2 1660
80  [temp]always-forever 무한루프 JMJS 08.10.2 1719
79  YCbCr2RGB.v JMJS 10.5.12 1943
78  [VHDL]rom64x8 JMJS 09.3.27 1547
77  [function]vector_compare JMJS 02.6.19 1515
76  [function]vector2integer JMJS 02.6.19 1584
75  [VHDL]ram8x4x8 JMJS 08.12.1 1449
74  [예]shift JMJS 02.6.19 1825
73  test JMJS 09.7.20 1578
72  test JMJS 09.7.20 1400
71  test JMJS 09.7.20 1347
70  test JMJS 09.7.20 1434
69  test JMJS 09.7.20 1469
68  test JMJS 09.7.20 1396
67  test JMJS 09.7.20 1314
66  test JMJS 09.7.20 1281
65  test JMJS 09.7.20 1377
64  test JMJS 09.7.20 1654
63  test JMJS 09.7.20 1643
62  test JMJS 09.7.20 1567
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3486
60  test JMJS 09.7.20 1298
59  test JMJS 09.7.20 1394
58  test JMJS 09.7.20 1430
57  test JMJS 09.7.20 1348
56  test JMJS 09.7.20 1393
55  verilog 학과 샘플강의 JMJS 16.5.30 2100
54  [verilog]create_generated_clock JMJS 15.4.28 2003
53  [Verilog]JDIFF JMJS 14.7.4 1269
52  [verilog]parameter definition JMJS 14.3.5 1520
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4502
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2259
49  Verdi JMJS 10.4.22 2929
48  draw hexa JMJS 10.4.9 1610
47  asfifo - Async FIFO JMJS 10.4.8 1434
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3115
45  synplify batch JMJS 10.3.8 2196
44  전자시계 Type A JMJS 08.11.28 1693
43  I2C Webpage JMJS 08.2.25 1559
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5989
41  [Verilog]vstring JMJS 17.9.27 1800
40  Riviera Simple Case JMJS 09.4.29 2981
39  [VHDL]DES Example JMJS 07.6.15 2684
38  [verilog]RAM example JMJS 09.6.5 2477
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1701
36  Jamie's VHDL Handbook JMJS 08.11.28 2354
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2985
34  RTL Job JMJS 09.4.29 1842
33  [VHDL]type example - package TYPES JMJS 06.2.2 1534
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9532
30  [verilog]array_module JMJS 05.12.8 1916
29  [verilog-2001]generate JMJS 05.12.8 3154
28  protected JMJS 05.11.18 1731
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2580
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1619
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2169
23  Array Of Array JMJS 04.8.16 1741
22  dumpfile, dumpvars JMJS 04.7.19 3367
21  Vending Machine Jamie 02.12.16 9978
20  Mini Vending Machine1 Jamie 02.12.10 6700
19  Mini Vending Machine Jamie 02.12.6 9631
18  Key Jamie 02.11.29 4745
17  Stop Watch Jamie 02.11.25 5464
16  Mealy Machine Jamie 02.8.29 6526
15  Moore Machine Jamie 02.8.29 17229
14  Up Down Counter Jamie 02.8.29 3751
13  Up Counter Jamie 02.8.29 2474
12  Edge Detecter Jamie 02.8.29 2735
11  Concept4 Jamie 02.8.28 1821
10  Concept3 Jamie 02.8.28 1776
9  Concept2_1 Jamie 02.8.28 1673
8  Concept2 Jamie 02.8.28 1741
7  Concept1 Jamie 02.8.26 1967
6  Tri State Buffer Jamie 02.8.26 3270
5  8x3 Encoder Jamie 02.8.28 3919
4  3x8 Decoder Jamie 02.8.28 3604
3  4bit Comparator Jamie 02.8.26 2961
2  가위 바위 보 게임 Jamie 02.8.26 5371
1  Two Input Logic Jamie 02.8.26 2190
[1]